Manufacturing method of a pixel structure

• US 9,685,470 B2
• Filed: 11/18/2013
• Issued: 06/20/2017
• Est. Priority Date: 11/12/2013
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: Hao, Sikun
• Primary Examiner(s): Everhart, Caridad
• Assistant Examiner(s): LIU, MIKKA H
• Application Number:
  US14/349,281
• Publication Number:
  US 20160013219A1
• Time in Patent Office: 1,310 Days
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate

Abstract

The present invention provides a pixel structure and a manufacturing method thereof. The pixel structure includes: a transparent substrate (60), a gate line formed on the transparent substrate (60), a thin-film transistor formed on the transparent substrate (60), a data line (68) formed on the transparent substrate (60), a pixel electrode (62) formed on the transparent substrate (60) and the thin-film transistor, a passivation layer (64) formed on the pixel electrode (62), the transparent substrate (60), and the data line (68), and a common electrode (66) formed on the passivation layer (64). The passivation layer (64) includes: a first portion (72) located on the data line (68), a second portion (74) located on the pixel electrode (62), and a third portion (76) located on the transparent substrate (60) and arranged on two opposite sides of the data line (68). The first portion (72) of the passivation layer (64) has a thickness greater than a thickness of the second portion (74).

Claims

1. A manufacturing method of a pixel structure, comprising the following steps:

providing a transparent substrate;

depositing a data line and a pixel electrode on the transparent substrate;

depositing a passivation layer on the transparent substrate, the data line, and the pixel electrode, wherein the passivation layer comprises;

a first portion located on the data line, a second portion located on the pixel electrode, and a third portion located on the transparent substrate and arranged on two opposite sides of the data line, a part of the third portion being located between and connecting between the first portion and the second portion;

subjecting the passivation layer to etching to reduce a thickness of the second portion of the passivation layer such that a thickness of the first portion of the passivation layer is greater than a thickness of the second portion and also, the thickness of the first portion of the passivation layer is greater than a thickness of the third portion and a top of the second portion of the passivation layer is flush with a top of the part of the third portion connecting between the first portion and the second portion, wherein the top of the second portion and the top of the part of the third portion collectively define a flat surface extending continuously to an edge of the first portion; and

depositing a common electrode on the passivation layer such that a portion of the common electrode that corresponds to a portion of the pixel electrode is laid flat directly on the flat surface defined collectively by the top of the second portion and the top of the part of the third portion.

2. The manufacturing method of the pixel structure as claimed in claim 1, wherein the pixel electrode is a transparent conductive layer and the common electrode is a transparent conductive layer.