Semiconductor device and method of forming IPD on molded substrate

• US 9,685,495 B2
• Filed: 03/18/2012
• Issued: 06/20/2017
• Est. Priority Date: 11/19/2009
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Inventors: Lin, Yaojian
• Primary Examiner(s): Naraghi, Ali
• Application Number:
  US13/423,265
• Publication Number:
  US 20120175735A1
• Time in Patent Office: 1,920 Days
• Field of Search: None
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 23/145 Organic substrates, e.g. plastic
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 27/016 Thin-film circuits
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/24 with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor device is made by depositing an encapsulant material between first and second plates of a chase mold to form a molded substrate. A first conductive layer is formed over the molded substrate. A resistive layer is formed over the first conductive layer. A first insulating layer is formed over the resistive layer. A second insulating layer is formed over the first insulating layer, resistive layer, first conductive layer, and molded substrate. A second conductive layer is formed over the first insulating layer, resistive layer, and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. The first conductive layer, resistive layer, first insulating layer, and second conductive layer constitute a MIM capacitor. The second conductive layer is wound to exhibit inductive properties.

Claims

1. A method of making a semiconductor device, comprising:

disposing a first conductive layer in a mold;

forming a substrate by curing a molding compound in the mold over the first conductive layer;

forming a first insulating layer over the first conductive layer;

forming a second conductive layer over the first insulating layer to form a capacitor with the first conductive layer; and

forming an interconnect structure electrically connected to the second conductive layer.

2. The method of claim 1, further including forming a resistive layer over the first conductive layer.

3. The method of claim 1, wherein forming the interconnect structure includes forming a bump or bond wire electrically connected to the capacitor.

4. The method of claim 1, further including depositing the molding compound between a first plate and second plate of the mold.

5. The method of claim 4, further including:

applying a first releasable layer over the first plate; and

applying a second releasable layer over the second plate.

6. The method of claim 1, further including forming a third conductive layer over the substrate and wound to exhibit inductive properties.

7. A method of making a semiconductor device, comprising:

disposing a second conductive layer in a mold;

forming a molded substrate by curing an encapsulant in the mold over the second conductive layer;

forming a first insulating layer over the molded substrate and second conductive layer;

forming a first conductive layer over the first insulating layer and wound to exhibit inductive properties; and

forming an interconnect structure over the first conductive layer opposite the molded substrate with the interconnect structure electrically connected to the first conductive layer.

8. The method of claim 7, further including:

forming a second insulating layer over the second conductive layer; and

forming a third conductive layer over the second insulating layer and second conductive layer as a capacitor.

9. The method of claim 8, further including forming a resistive layer over the second conductive layer.

10. The method of claim 8, wherein a coefficient of thermal expansion of the molded substrate is similar to a coefficient of thermal expansion of the first conductive layer.

11. The method of claim 7, wherein the interconnect structure includes a bump or bond wire.

12. The method of claim 7, wherein forming the molded substrate includes:

providing the mold to include a first plate and a second plate;

forming a first releasable layer over the first plate;

forming a second releasable layer over the second plate;

forming the second conductive layer on the second releasable layer; and

depositing the encapsulant between the first plate and second plate of the mold.

13. A method of making a semiconductor device, comprising:

disposing a first conductive layer in a mold;

forming a substrate by curing a molding compound in the mold over the first conductive layer;

forming an integrated passive device (IPD) over the substrate after forming the substrate in the mold; and

forming an interconnect structure over the IPD.

14. The method of claim 13, wherein forming the IPD includes forming a second conductive layer over the substrate and wound to exhibit inductive properties.

15. The method of claim 13, wherein forming the IPD includes:

forming a first insulating layer over the first conductive layer; and

forming a second conductive layer over the first insulating layer and first conductive layer as a capacitor.

16. The method of claim 13, further including forming a resistive layer over the first conductive layer.

17. The method of claim 13, wherein a coefficient of thermal expansion of the substrate is similar to a coefficient of thermal expansion of the IPD.

18. The method of claim 13, wherein the interconnect structure includes a bump or bond wire electrically connected to the IPD.

19. The method of claim 13, wherein forming the substrate includes depositing an encapsulant between a first plate and second plate of the mold.

20. A semiconductor device, comprising:

a molded substrate;

a first conductive layer formed directly on the molded substrate and partially within a cavity of the molded substrate;

an integrated passive device (IPD) including the first conductive layer as a part of the IPD; and

an interconnect structure electrically connected to the IPD.

21. The semiconductor device of claim 20, wherein the IPD further includes a second conductive layer formed over the molded substrate and wound to exhibit inductive properties.

22. The semiconductor device of claim 20, wherein the IPD further includes:

a first insulating layer formed over the first conductive layer; and

a second conductive layer formed over the first insulating layer and first conductive layer as a capacitor.

23. The semiconductor device of claim 22, further including a resistive layer formed over the first conductive layer.

24. The semiconductor device of claim 20, further including:

a chase mold including a first plate and second plate; and

an encapsulant deposited between the first plate and second plate of the chase mold.