Circuit system

• US 9,685,500 B2
• Filed: 03/12/2015
• Issued: 06/20/2017
• Est. Priority Date: 03/14/2014
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Hondo, Suguru, Shionoiri, Yutaka, Nagatsuka, Shuhei, Atsumi, Tomoaki, Okazaki, Yutaka, Yamazaki, Shunpei
• Primary Examiner(s): Roman, Angel
• Application Number:
  US14/645,566
• Publication Number:
  US 20150263007A1
• Time in Patent Office: 831 Days
• Field of Search: None
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A semiconductor device with a transistor having favorable electrical characteristics is provided. The semiconductor device has a memory circuit and a circuit that are over the same substrate. The memory circuit includes a capacitor, a first transistor, and a second transistor. A gate of the first transistor is electrically connected to the capacitor and one of a source and a drain of the second transistor. The circuit includes a third transistor and a fourth transistor that are electrically connected to each other in series. The first transistor and the third transistor each include an active layer including silicon, and the second transistor and the fourth transistor each include an active layer including an oxide semiconductor.

Claims

1. A semiconductor device comprising:

a capacitor; and

a transistor electrically connected to the capacitor,

wherein electrostatic capacitance of the capacitor is larger than or equal to 0.1 fF and less than 10 fF,

wherein the transistor comprises an oxide semiconductor film, and

wherein writing time of the semiconductor device is longer than or equal to 0.1 nsec and shorter than 5 nsec in operation at room temperature.

2. The semiconductor device according to claim 1,

wherein the oxide semiconductor film comprises crystal parts aligned in a c-axis direction.

3. A semiconductor device comprising:

a memory circuit over a substrate, the memory circuit comprising a capacitor, a first transistor, and a second transistor; and

a circuit over the substrate, the circuit comprising a third transistor and a fourth transistor,

wherein a gate of the first transistor is electrically connected to the capacitor and one of a source and a drain of the second transistor,

wherein the third transistor and the fourth transistor are electrically connected to each other in series,

wherein the first transistor and the third transistor each comprise an active layer comprising silicon, and

wherein the second transistor and the fourth transistor each comprise an active layer of an oxide semiconductor film.

4. The semiconductor device according to claim 3,

wherein the first transistor and the third transistor are p-channel transistors.

5. The semiconductor device according to claim 3,

wherein the second transistor has a region in which a channel length is larger than or equal to 1 nm and less than 100 nm, and

wherein the fourth transistor has a region in which a channel length is larger than or equal to 1 nm and less than 100 nm.

6. The semiconductor device according to claim 3,

wherein the second transistor has a region in which a channel length is larger than or equal to 5 nm and less than 60 nm, and

wherein the fourth transistor has a region in which a channel length is larger than or equal to 5 nm and less than 60 nm.

7. The semiconductor device according to claim 3,

wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the capacitor are three-dimensionally arranged.

8. The semiconductor device according to claim 3,

wherein electrostatic capacitance of the capacitor is larger than or equal to 0.1 fF and less than 10 fF.

9. The semiconductor device according to claim 3,

wherein writing time of the memory circuit is longer than or equal to 0.1 nsec and shorter than 5 nsec.

10. The semiconductor device according to claim 3,

wherein the oxide semiconductor film contains oxygen, In, Zn, and one of Ti, Ga, Y, Zr, La, Ce, Nd, and Hf.

11. The semiconductor device according to claim 3,

wherein the oxide semiconductor film comprises crystal parts.

12. The semiconductor device according to claim 3,

wherein the oxide semiconductor film comprises crystal parts aligned in a c-axis direction.

13. A semiconductor device comprising:

a memory circuit over a substrate, the memory circuit comprising a capacitor, a first transistor, and a second transistor; and

a circuit over the substrate, the circuit comprising a third transistor and a fourth transistor,

wherein a gate of the first transistor is electrically connected to the capacitor and one of a source and a drain of the second transistor,

wherein the third transistor and the fourth transistor are electrically connected to each other in series, and

wherein the first transistor, the second transistor, the third transistor, and the fourth transistor each comprise an active layer of an oxide semiconductor film.

14. The semiconductor device according to claim 13,

wherein the first transistor, the second transistor, the third transistor, and the fourth transistor each have a region in which a channel length is larger than or equal to 1 nm and less than 100 nm.

15. The semiconductor device according to claim 13,

wherein the first transistor, the second transistor, the third transistor, and the fourth transistor each have a region in which a channel length is larger than or equal to 5 nm and less than 60 nm.

16. The semiconductor device according to claim 13,

wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the capacitor are three-dimensionally arranged.

17. The semiconductor device according to claim 13,

wherein electrostatic capacitance of the capacitor is larger than or equal to 0.1 fF and less than 10 fF.

18. The semiconductor device according to claim 13,

wherein writing time of the memory circuit is longer than or equal to 0.1 nsec and shorter than 5 nsec.

19. The semiconductor device according to claim 13,

wherein the oxide semiconductor film contains oxygen, In, Zn, and one of Ti, Ga, Y, Zr, La, Ce, Nd, and Hf.

20. The semiconductor device according to claim 13,

wherein the oxide semiconductor film comprises crystal parts.

21. The semiconductor device according to claim 13,

wherein the oxide semiconductor film comprises crystal parts aligned in a c-axis direction.