Half bridge power conversion circuits using GaN devices

• US 9,685,869 B1
• Filed: 11/23/2016
• Issued: 06/20/2017
• Est. Priority Date: 09/16/2014
• Status: Active Grant

• Current Assignee: Navitas Semiconductor, Inc.
• Original Assignee: Navitas Semiconductor, Inc.
• Inventors: Kinzer, Daniel M., Sharma, Santosh, Zhang, Ju Jason
• Primary Examiner(s): Mehari, Yemane
• Application Number:
  US15/360,123
• Time in Patent Office: 209 Days
• Field of Search: 323132, 323271, 323272
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02J 7/00 Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
• CPC Class Codes: H02M 1/0048 : Circuits or arrangements for reducing losses using snubbers H02M1/34
• CPC Class Codes: H02M 1/088 : for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H02M 3/155 : using semiconductor devices only
• CPC Class Codes: H02M 3/157 : with digital control
• CPC Class Codes: H02M 3/1584 : with a plurality of power processing stages connected in parallel
• CPC Class Codes: H02M 3/1588 : comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 17/102 : in field-effect transistor switches
• CPC Class Codes: H03K 19/018507 : Interface arrangements
• CPC Class Codes: H03K 3/012 : Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356017 : using additional transistors in the input circuit H03K3/356104, H03K3/3562 take precedence
• CPC Class Codes: Y02B 40/00 : Technologies aiming at improving the efficiency of home appliances, e.g. induction cooking or efficient technologies for refrigerators, freezers or dish washers
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.

Claims

1. A half bridge circuit comprising:

a GaN-based low side circuit including;

a GaN-based low side switch having a low side switch control gate, a low side switch source and a low side switch drain, wherein the low side switch source is coupled to a ground and the low side switch drain is connected to a switch node; and

a GaN-based low side switch driver having an output coupled to the low side switch control gate;

a GaN-based high side circuit including;

a GaN-based high side switch having a high side control gate, a high side switch source and a high side switch drain, wherein the high side switch source is coupled to the switch node and the high side switch drain is coupled to a voltage source; and

a GaN-based high side switch driver having an output coupled to the high side switch control gate and an input coupled to a level shift circuit;

a blanking pulse circuit configured to generate a signal that controls a state of at least one of the GaN-based low side switch and the GaN-based high side switch;

a state storage device that is configured to change a stored state corresponding to on and off states of the GaN-based high side switch driver; and

an under voltage lock out circuit configured to prevent drive signals from reaching the input of the GaN-based high side switch driver when a circuit supply voltage is less than a threshold voltage.

2. The half bridge circuit of claim 1 wherein the blanking pulse circuit is configured to generate a pulse signal that corresponds to a turn off transient of the GaN-based low side switch to prevent turn-on of the GaN-based high side switch.

3. The half bridge circuit of claim 1 wherein the state storage device is a flip-flop device.

4. The half bridge circuit of claim 1 wherein the GaN-based low side circuit and the GaN-based high side circuit are disposed on a single monolithic GaN-based device.

5. The half bridge circuit of claim 1 wherein the GaN-based low side circuit is disposed on a first monolithic GaN-based device and the GaN-based high side circuit is disposed on a second monolithic GaN-based device.

6. The half bridge circuit of claim 1 further comprising a boot strap transistor configured to conduct when the GaN-based low side switch is in an on state.

7. The half bridge circuit of claim 1 wherein at least one of the GaN-based low side circuit and the GaN-based high side circuit have an ESD protection circuit.

8. The half bridge circuit of claim 1 wherein all transistors within the GaN-based low side circuit and within the GaN-based high side circuit are enhancement mode devices.

9. The half bridge circuit of claim 1 wherein all inverters and gates within the GaN-based low side circuit and within the GaN-based high side circuit are enhancement mode transistors.

10. The half bridge circuit of claim 1 wherein all inverters and gates within the GaN-based low side circuit and within the GaN-based high side circuit use charge pump capacitors to drive gates of pull-up transistors above a positive rail voltage.

11. A method of operating a half bridge power conversion circuit, the method comprising:

operating a low side switch using a low side driver, wherein the low side switch and the low side driver comprise a first GaN-based circuit;

operating a high side switch using a high side driver, wherein the high side switch and the high side driver comprise a second GaN-based circuit;

controlling the low side driver and the high side driver with a control circuit that transmits on and off signals to the low side and the high side drivers;

generating a blanking pulse to control a state of at least one of the GaN-based low side switch and the GaN-based high side switches;

changing a state of a state storage device corresponding to on and off states of the GaN-based high side switch driver;

transmitting a drive signal to an input of the high side driver with a level shift circuit; and

preventing the high side driver from operating the high side switch when a circuit supply voltage is less than a threshold voltage.

12. The method of claim 11 wherein the blanking pulse corresponds to a turn off transient of the GaN-based low side switch to prevent turn-on of the GaN-based high side switch.

13. The method of claim 11 wherein the state storage device is a flip-flop device.

14. The method of claim 11 wherein the GaN-based low side switch and the GaN-based high side switch are disposed on a single monolithic GaN-based device.

15. The method of claim 11 wherein the GaN-based low side switch is disposed on a first GaN-based device and the GaN-based high side switch is disposed on a second GaN-based device.

16. An electronic package including one or more semiconductor devices that form a circuit comprising:

a GaN-based low side circuit including;

a GaN-based low side switch having a low side switch control gate, a low side switch source and a low side switch drain, wherein the low side switch source is coupled to a ground and the low side switch drain is connected to a switch node; and

a GaN-based low side switch driver having an output coupled to the low side switch control gate;

a GaN-based high side circuit including;

a GaN-based high side switch having a high side control gate, a high side switch source and a high side switch drain, wherein the high side switch source is coupled to the switch node and the high side switch drain is coupled to a voltage source; and

a GaN-based high side switch driver having an output coupled to the high side switch control gate and an input coupled to a level shift circuit;

a blanking pulse circuit configured to generate a signal that controls a state of at least one of the GaN-based low side switch and the GaN-based high side switch;

a state storage device that is configured to change a stored state corresponding to on and off states of the GaN-based high side switch driver; and

an under voltage lock out circuit configured to prevent drive signals from reaching the input of the GaN-based high side switch driver when a circuit supply voltage is less than a threshold voltage.

17. The electronic package of claim 16 wherein the blanking pulse circuit is configured to generate a pulse signal that corresponds to a turn off transient of the GaN-based low side switch to prevent turn-on of the GaN-based high side switch.

18. The electronic package of claim 16 wherein the state storage device is a flip-flop device.

19. The electronic package of claim 16 wherein the GaN-based low side circuit and the GaN-based high side circuit are disposed on a single monolithic GaN-based device.

20. The electronic package of claim 16 wherein the GaN-based low side circuit is disposed on a first GaN-based device and the GaN-based high side circuit is disposed on a second GaN-based device.