End of communication detection

• US 9,686,041 B2
• Filed: 08/31/2015
• Issued: 06/20/2017
• Est. Priority Date: 12/20/2013
• Status: Expired due to Fees

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: van de Beek, Remco, Ciacci, Massimo, Al-kadi, Ghiath
• Primary Examiner(s): Tsvey, Gennadiy
• Application Number:
  US14/841,644
• Publication Number:
  US 20150372787A1
• Time in Patent Office: 659 Days
• CPC Class Codes: G06K 19/067 Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
• CPC Class Codes: H04B 5/266 One coil at each side, e.g. with primary and secondary coils
• CPC Class Codes: H04B 5/72 for local intradevice communication
• CPC Class Codes: H04B 5/77 for interrogation
• CPC Class Codes: H04L 1/0039 other detection of signalling, e.g. detection of TFCI explicit signalling H04L1/0046, H04L27/0012 and H04L25/0262 take precedence
• CPC Class Codes: H04L 2027/0036 using a recovered symbol clock
• CPC Class Codes: H04L 2027/0057 quadrature phase
• CPC Class Codes: H04L 2027/0095 in a preamble or similar structure
• CPC Class Codes: H04L 27/22 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 27/227 using coherent demodulation
• CPC Class Codes: H04L 27/2271 wherein the carrier recovery circuit uses only the demodulated signals
• CPC Class Codes: H04L 27/2272 using phase locked loops H04L27/2273 takes precedence
• CPC Class Codes: H04L 27/2273 associated with quadrature demodulation, e.g. Costas loop
• CPC Class Codes: H04L 5/001 the frequencies being arranged in component carriers
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal
• CPC Class Codes: H04L 7/042 Detectors therefor, e.g. correlators, state machines digital correlators in general G06F17/15

Abstract

An apparatus for detecting the end of a communication is disclosed. The apparatus includes an interface circuit for receiving an encoded signal and a carrier signal recovery circuit coupled to an output of the interface circuit. The carrier signal recovery circuit is configured to output a carrier signal of the encoded signal and a second signal that is out of phase with the carrier signal. The apparatus also includes a decoding circuit configured to decode the encoded signal as a function of both the encoded signal and the carrier signal output by the carrier signal recovery circuit. The apparatus also includes a detection circuit configured to detect an indication of an end of a communication in the encoded signal as a function of both the encoded signal and the second signal.

Claims

1. An apparatus, comprising:

a carrier signal recovery circuit configured and arranged to receive an encoded signal and to respond by

determining and outputting a carrier signal of the encoded signal, and

generating and outputting a second signal that is out of phase with the carrier signal; and

circuitry coupled to the carrier signal recovery circuit and configured and arranged to decode the encoded signal as a function of the encoded signal and the carrier signal output by the carrier signal recovery circuit and to detect an indication of an end of a communication in the encoded signal as a function of the encoded signal and the second signal by sampling values of the second signal at times relative to an edge of the encoded signal being received.

2. The apparatus of claim 1, wherein the second signal is 90 degrees out of phase with the carrier signal, and wherein the circuitry includes a circuit configured and arranged to detect the edge of the encoded signal.

3. The apparatus of claim 1, wherein the encoded and second signals correspond to two quadrature signals derived from the carrier signal, and wherein the circuitry is further configured and arranged to compare the second signal with the encoded signal.

4. The apparatus of claim 1, further including a phase-locked-loop circuit and wherein the circuitry includes a frequency divider following the phase-locked-loop circuit, and wherein the encoded and second signals correspond to two quadrature signals derived from the carrier signal by the phase-locked-loop circuit.

5. The apparatus of claim 1, wherein the carrier signal recovery circuit includes a phase-locked-loop (PLL) circuit.

6. The apparatus of claim 1, wherein the carrier signal recovery circuit includes a phase-locked-loop (PLL) circuit and further includes a frequency divider coupled to an output of the PLL circuit.

7. The apparatus of claim 1, wherein the circuitry coupled to the carrier signal recovery circuit includes a time-to-digital converter.

8. The apparatus of claim 1, wherein the encoded signal is a phase-shift-key (PSK) encoded signal.

9. The apparatus of claim 1, further including a loop antenna, configured and arranged before the carrier signal recovery circuit for providing the encoded signal to the carrier signal recovery circuit.

10. The apparatus of claim 1, further including

a power supply coupled to a loop antenna and configured and arranged to generate a power supply voltage from electro-magnetic signals received by the loop antenna;

the loop antenna, configured and arranged before the carrier signal recovery circuit for providing the encoded signal to the carrier signal recovery circuit;

a phase-locked-loop circuit;

a frequency divider including within the circuitry and following the phase-locked-loop circuit, and wherein the encoded and second signals correspond to two quadrature signals derived from the carrier signal by the phase-locked-loop circuit; and

a signal amplification circuit configured and arranged with input ports coupled to the loop antenna and configured and arranged to provide a signal corresponding to the encoded signal received by the carrier signal recovery circuit.

11. The apparatus of claim 10, wherein the circuitry includes a flip-flop having an input terminal connected to receive the encoded signal and having a clock terminal connected to receive the second signal from the carrier signal recovery circuit.

12. The apparatus of claim 10, wherein the circuitry includes a flip-flop having an input terminal connected to receive the encoded signal and having a clock terminal connected to receive the second signal from the carrier signal recovery circuit and further includes a logical inverter circuit having an input coupled to an output of the flip-flop and an output coupled to an output of the circuitry.

13. The apparatus of claim 1, wherein the circuitry includes a flip-flop having an input terminal connected to receive the second signal from the carrier signal recovery circuit and having a clock terminal connected to receive a signal corresponding to the encoded signal, and further including

a power supply coupled to a loop antenna and configured and arranged to generate a power supply voltage from electro-magnetic signals received by the loop antenna;

the loop antenna, configured and arranged for near-field communication and further configured and arranged before the carrier signal recovery circuit for providing the encoded signal to the carrier signal recovery circuit;

a phase-locked-loop circuit;

a frequency divider including within the circuitry and following the phase-locked-loop circuit, and wherein the encoded and second signals correspond to two quadrature signals derived from the carrier signal by the phase-locked-loop circuit; and

a signal amplification circuit configured and arranged with input ports coupled to the loop antenna and configured and arranged to provide a signal corresponding to the encoded signal received by the carrier signal recovery circuit.

14. The apparatus of claim 13, wherein the carrier signal recovery circuit includes a phase-locked-loop (PLL) circuit.

15. The apparatus of claim 13, wherein the carrier signal recovery circuit includes a phase-locked-loop (PLL) circuit and further includes a frequency divider coupled to an output of the PLL circuit.

16. The apparatus of claim 13, wherein the circuitry includes a time-to-digital converter.

17. The apparatus of claim 13, wherein the encoded signal is a phase-shift-key (PSK) encoded signal.

18. A method of wireless data communication, comprising:

receiving over an antenna a wireless signal;

determining, in response to receiving the wireless signal, a carrier signal of an encoded signal;

phase shifting the carrier signal to produce a second signal that is out of phase with the carrier signal;

decoding the encoded signal as a function of the encoded signal and the carrier signal; and

detecting whether or not the encoded signal includes an indication of an end of a communication in the encoded signal by comparing the second signal with the encoded signal.

19. The method of claim 18, wherein the wireless signal is conveyed using near-field communication and the encoded signal is a phase-shift-key encoded signal and further comprising:

in response to the second signal having a first value at a time in which an edge of the encoded signal is detected, signaling that the indication of an end of a communication is not received; and

in response to the second signal having a second value at a time in which an edge of the encoded signal is detected, signaling that the indication that an end of a communication is received.