Methods and systems for chip-to-chip communication with reduced simultaneous switching noise
First Claim
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1. An apparatus comprising:
- an encoder configured to receive a set of n bits, wherein n is a predetermined integer greater than or equal to 3, and to encode the set of n bits to a vector signaling code word as transitions from a previously transmitted vector signaling code word having a plurality of elements of three or more levels in the transmission interface, wherein the encoder is configured to check less than n bits of set of n bits for a first logic condition that if satisfied, configures the encoder to transition a level of a single element of the previously transmitted vector signaling code word according to a first transition-limiting function operating on a prior state of the level of the single element, and if the first logic condition fails, the encoder is configured to check less than n bits of the set of n bits for a second logic condition that if satisfied, configures the encoder to transition levels of two elements of the previously transmitted vector signaling code word according to a second transition-limiting function operating on prior states of the levels of the two elements; and
an output driver circuit configured to provide the vector signaling codeword in one transmission interval on a multi-wire bus.
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Abstract
Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.
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20 Claims
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1. An apparatus comprising:
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an encoder configured to receive a set of n bits, wherein n is a predetermined integer greater than or equal to 3, and to encode the set of n bits to a vector signaling code word as transitions from a previously transmitted vector signaling code word having a plurality of elements of three or more levels in the transmission interface, wherein the encoder is configured to check less than n bits of set of n bits for a first logic condition that if satisfied, configures the encoder to transition a level of a single element of the previously transmitted vector signaling code word according to a first transition-limiting function operating on a prior state of the level of the single element, and if the first logic condition fails, the encoder is configured to check less than n bits of the set of n bits for a second logic condition that if satisfied, configures the encoder to transition levels of two elements of the previously transmitted vector signaling code word according to a second transition-limiting function operating on prior states of the levels of the two elements; and an output driver circuit configured to provide the vector signaling codeword in one transmission interval on a multi-wire bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method comprising:
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receiving a set of n bits, wherein n is a predetermined integer greater than or equal to 3; encoding the set of n bits into a vector signaling codeword as transitions from a previously transmitted vector signaling codeword comprising a plurality of elements of three or more values, wherein the encoding comprises checking one or more bits for a first logic condition that if satisfied, transitions a value of a single element of the previously transmitted vector signaling codeword according to a first transition-limiting function operating on a prior state of the value of the single element, and if the first logic condition fails, checking less than n bits for a second logic condition that if satisfied, transitions values of two elements of the previously transmitted vector signaling codeword according to a second transition-limiting function operating on prior states of the levels of the two elements; and transmitting the vector signaling code word in one transmission interval on a set of wires. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification