Adaptive electrical testing of wafers

• US 9,689,923 B2
• Filed: 08/01/2014
• Issued: 06/27/2017
• Est. Priority Date: 08/03/2013
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation
• Original Assignee: KLA-Tencor Corporation
• Inventors: Kekare, Sagar A.
• Primary Examiner(s): Parihar, Suchin
• Application Number:
  US14/450,027
• Publication Number:
  US 20150039954A1
• Time in Patent Office: 1,061 Days
• Field of Search: 716136
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

A method and a system for determining one or more parameters for electrical testing of a wafer are provided. One method includes determining electrical test paths through a device being formed on a wafer and physical layout components in different layers of the device corresponding to each of the electrical test paths. The method also includes determining one or more parameters of electrical testing for the wafer based on one or more characteristics of the electrical test paths. In addition, the method includes acquiring information for one or more characteristics of a physical version of the wafer. The information is generated by performing an inline process on the physical version of the wafer. The method further includes altering at least one of the one or more parameters of the electrical testing for the wafer based on the acquired information.

Claims

1. A computer-implemented method for determining one or more parameters for electrical testing of a wafer, comprising:

determining a plurality of electrical test paths through a device being formed on a wafer and physical layout components in different layers of the device corresponding to each of the plurality of electrical test paths;

determining one or more parameters of electrical testing for the wafer based on one or more characteristics of the plurality of electrical test paths;

acquiring information for one or more characteristics of a physical version of the wafer, wherein the information is generated by a process control system performing an inline process on the physical version of the wafer;

altering at least one of the one or more parameters based on the acquired information, wherein determining the plurality of electrical test paths, determining the one or more parameters, acquiring the information, and altering the at least one parameter are performed by a computer system, and wherein the computer system is a device having one or more processors; and

performing the electrical testing on the wafer with electrical testing equipment and the altered at least one of the one or more parameters.

2. The method of claim 1, wherein the one or more characteristics of the plurality of electrical test paths comprise a pareto of the plurality of electrical test paths as a function of fractions of layout lengths for the plurality of electrical test paths on one of the different layers.

3. The method of claim 1, wherein the one or more characteristics of the plurality of electrical test paths comprise different paretos for each of the different layers of interest, and wherein each of the different paretos are of the plurality of electrical test paths as a function of fractions of layout lengths for the plurality of electrical test paths on its corresponding one of the different layers.

4. The method of claim 1, wherein the one or more parameters comprise test vector sequences that stress one of the different layers in a preferential manner.

5. The method of claim 1, wherein the one or more parameters comprise different test vector sequences for each of the different layers that are of interest to a user, and wherein the different test vector sequences are for stressing each of the different layers in a preferential manner.

6. The method of claim 1, wherein the one or more parameters comprise different test vector sequences for each of the different layers that are of interest to a user, and wherein the different test vector sequences are for stressing each of the different layers in a preferential manner and based on design sub-sections within the different layers.

7. The method of claim 1, further comprising storing the one or more parameters in a storage medium, wherein the one or more parameters comprise test vector sequences in different test plans for the wafer, and wherein each of the different test plans is stored with identification for the different layers or different design sub-sections within the different layers that the different test plans stress preferentially.

8. The method of claim 1, wherein the process control system comprises a wafer inspection system or a wafer defect review system, and wherein the information for the one or more characteristics of the physical version of the wafer comprises information for defects detected on the physical version of the wafer by the wafer inspection system or the wafer defect review system.

9. The method of claim 1, wherein the process control system comprises a wafer metrology system, and wherein the information for the one or more characteristics of the physical version of the wafer comprises measurements of the one or more characteristics performed on the physical version of the wafer by the wafer metrology system.

10. The method of claim 1, wherein process steps of fabrication of the device on the wafer are performed, and wherein the inline process is performed during one of the process steps or between the process steps of the fabrication of the device on the wafer.

11. The method of claim 1, wherein the information for the one or more characteristics of the physical version of the wafer comprises information for which of the different layers on which the inline process was performed.

12. The method of claim 1, wherein the information for the one or more characteristics of the physical version of the wafer comprises information for locations within any one of the different layers at which the one or more characteristics of the physical version of the wafer were determined by the inline process.

13. The method of claim 1, wherein the information is further generated by performing at least one additional inline process on the wafer.

14. The method of claim 1, wherein altering the at least one parameter comprises selecting an order in which different tests are performed during the electrical testing.

15. The method of claim 1, wherein altering the at least one parameter comprises selecting a test vector sequence for the electrical testing that stresses one of the different layers or a portion of one of the different layers in which the information for the one or more characteristics of the physical version of the wafer indicate one or more defects have been detected.

16. The method of claim 1, wherein the information for the one or more characteristics of the physical version of the wafer comprises information for a portion of the physical layout components in the different layers that have one or more characteristics that are different from their as-designed one or more characteristics, and wherein altering the at least one parameter comprises selecting one or more of the plurality of electrical test paths that contain the portion of the physical layout components as a highest priority for the electrical testing and one or more of the plurality of electrical test paths that contain physical layout components neighboring the portion of the physical layout components as a next highest priority for the electrical testing.

17. The method of claim 1, wherein altering the at least one parameter is not performed until the physical version of the wafer has been created and at least the inline process has been performed on the wafer.

18. The method of claim 1, wherein determining the plurality of electrical test paths through the device being formed on the wafer and the physical layout components in the different layers of the device corresponding to each of the plurality of electrical test paths is performed by processing design data for the device being formed on the wafer.

19. A non-transitory computer-readable medium, storing program instructions executing on a computer system for performing a computer-implemented method for determining one or more parameters for electrical testing of a wafer, wherein the computer-implemented method comprises:

determining a plurality of electrical test paths through a device being formed on a wafer and physical layout components in different layers of the device corresponding to each of the plurality of electrical test paths based on design data for the device;

determining one or more parameters of electrical testing for the wafer based on one or more characteristics of the plurality of electrical test paths;

acquiring information for one or more characteristics of a physical version of the wafer, wherein the information is generated by a process control system performing an inline process on the physical version of the wafer and wherein the information is acquired by the computer system from a storage medium in which the information has been stored by the process control system; and

altering at least one of the one or more parameters based on the acquired information, wherein the computer system is a device having one or more processors.

20. A system configured to determine one or more parameters for electrical testing of a wafer, comprising:

a process control subsystem configured to acquire information for one or more characteristics of a physical version of a wafer, wherein the information is generated by performing an inline process on the physical version of the wafer; and

a computer system configured for;

determining a plurality of electrical test paths through a device being formed on the wafer and physical layout components in different layers of the device corresponding to each of the plurality of electrical test paths based on design data for the device;

determining one or more parameters of electrical testing for the wafer based on one or more characteristics of the plurality of electrical test paths; and

altering at least one of the one or more parameters based on the acquired information, wherein the computer system is a device having one or more processors, and wherein electrical testing equipment is configured to perform the electrical testing on the wafer with the altered at least one of the one or more parameters.

21. The system of claim 20, wherein the one or more characteristics of the plurality of electrical test paths comprise a pareto of the plurality of electrical test paths as a function of fractions of layout lengths for the plurality of electrical test paths on one of the different layers.

22. The system of claim 20, wherein the one or more characteristics of the plurality of electrical test paths comprise different paretos for each of the different layers of interest, and wherein each of the different paretos are of the plurality of electrical test paths as a function of fractions of layout lengths for the plurality of electrical test paths on its corresponding one of the different layers.

23. The system of claim 20, wherein the one or more parameters comprise test vector sequences that stress one of the different layers in a preferential manner.

24. The system of claim 20, wherein the one or more parameters comprise different test vector sequences for each of the different layers that are of interest to a user, and wherein the different test vector sequences are for stressing each of the different layers in a preferential manner.

25. The system of claim 20, wherein the one or more parameters comprise different test vector sequences for each of the different layers that are of interest to a user, and wherein the different test vector sequences are for stressing each of the different layers in a preferential manner and based on design sub-sections within the different layers.

26. The system of claim 20, wherein the computer system is further configured for storing the one or more parameters in a storage medium, wherein the one or more parameters comprise test vector sequences in different test plans for the wafer, and wherein each of the different test plans is stored with identification for the different layers or different design sub-sections within the different layers that the different test plans stress preferentially.

27. The system of claim 20, wherein the process control subsystem comprises a wafer inspection system or a wafer defect review system, and wherein the information for the one or more characteristics of the physical version of the wafer comprises information for defects detected on the physical version of the wafer by the wafer inspection system or the wafer defect review system.

28. The system of claim 20, wherein the process control subsystem comprises a wafer metrology system, and wherein the information for the one or more characteristics of the physical version of the wafer comprises measurements of the one or more characteristics performed on the physical version of the wafer by the wafer metrology system.

29. The system of claim 20, wherein process steps of fabrication of the device on the wafer are performed, and wherein the inline process is performed during one of the process steps or between the process steps of the fabrication of the device on the wafer.

30. The system of claim 20, wherein the information for the one or more characteristics of the physical version of the wafer comprises information for which of the different layers on which the inline process was performed.

31. The system of claim 20, wherein the information for the one or more characteristics of the physical version of the wafer comprises information for locations within any one of the different layers at which the one or more characteristics of the physical version of the wafer were determined by the inline process.

32. The system of claim 20, wherein the information is further generated by performing at least one additional inline process on the wafer.

33. The system of claim 20, wherein altering the at least one parameter comprises selecting an order in which different tests are performed during the electrical testing.

34. The system of claim 20, wherein altering the at least one parameter comprises selecting a test vector sequence for the electrical testing that stresses one of the different layers or a portion of one of the different layers in which the information for the one or more characteristics of the physical version of the wafer indicate one or more defects have been detected.

35. The system of claim 20, wherein the information for the one or more characteristics of the physical version of the wafer comprises information for a portion of the physical layout components in the different layers that have one or more characteristics that are different from their as-designed one or more characteristics, and wherein altering the at least one parameter comprises selecting one or more of the plurality of electrical test paths that contain the portion of the physical layout components as a highest priority for the electrical testing and one or more of the plurality of electrical test paths that contain physical layout components neighboring the portion of the physical layout components as a next highest priority for the electrical testing.

36. The system of claim 20, wherein altering the at least one parameter is not performed until the physical version of the wafer has been created and at least the inline process has been performed on the wafer.