Saving power when in or transitioning to a static mode of a processor by using feedback-configured voltage regulator

• US 9,690,366 B2
• Filed: 08/19/2016
• Issued: 06/27/2017
• Est. Priority Date: 10/23/2000
• Status: Expired due to Fees

• Current Assignee: HD Silicon Solutions LLC (f/k/a Innovative Silicon Solutions, LLC)
• Original Assignee: Intellectual Ventures Holding 81 LLC (Intellectual Ventures LLC)
• Inventors: Halepete, Sameer, Klayman, Keith, Read, Andrew
• Primary Examiner(s): Cao, Chun
• Application Number:
  US15/241,690
• Publication Number:
  US 20160357247A1
• Time in Patent Office: 312 Days
• Field of Search: 713320, 713323
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method for reducing power utilized by a processor including the steps of determining that a processor is transitioning from a computing mode to a mode is which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled.

Claims

1. A circuit comprising:

an input terminal;

an output terminal;

a voltage regulator coupled to the input and output terminals and including a feedback terminal, wherein the voltage regulator is configured to provide a selected regulated voltage value from a range of regulated voltage values at the output terminal; and

a feedback circuit coupled to the output and feedback terminals and configured to reduce the selected regulated voltage value in response to a control signal to the feedback circuit.

2. The circuit of claim 1, wherein the feedback circuit comprises a control terminal configured to receive the control signal that controls a clock signal.

3. The circuit of claim 2, wherein if the control signal does not indicate the clock signal is to be stopped, the selected regulated voltage value is unaltered by the feedback circuit, and wherein if the control signal indicates the clock signal is to be stopped, the feedback circuit reduces the selected regulated voltage value.

4. The circuit of claim 2, wherein the feedback circuit is further configured to couple to a voltage source with a voltage value that is greater than the selected regulated voltage value.

5. The circuit of claim 4, wherein the feedback circuit comprises:

a first resistor including a first terminal coupled to the output terminal and a second terminal coupled to the feedback terminal;

a second resistor including a third terminal and a fourth terminal that is coupled to the feedback terminal and to the second terminal; and

a transistor including the control terminal, a terminal coupled to the third terminal, and another terminal configured to couple to the voltage source.

6. The circuit of claim 5, wherein the transistor is configured to provide an electrical connection between the terminal and the other terminal in response to the control signal.

7. The circuit of claim 1, wherein the voltage regulator further comprises:

a voltage selection terminal configured to receive a selection input to select the selected regulated voltage value, wherein the range includes a lowest regulated voltage value and a highest regulated voltage value.

8. A circuit comprising:

an input terminal;

an output terminal;

a voltage regulator coupled to the input and output terminals and including a feedback terminal, wherein the voltage regulator is configured to provide a selected regulated voltage value from a range of regulated voltage values at the output terminal;

a first resistor including a first terminal coupled to the output terminal and a second terminal coupled to the feedback terminal;

a second resistor including a third terminal and a fourth terminal that is coupled to the feedback terminal and to the second terminal; and

a transistor including a control terminal configured to receive a control signal, a terminal coupled to the third terminal, and another terminal configured to couple to a voltage source with a voltage value that is greater than the selected regulated voltage value.

9. The circuit of claim 8, wherein the first resistor, the second resistor, and the transistor are arranged as a feedback circuit.

10. The circuit of claim 9, wherein if the control signal does not indicate a clock signal is to be stopped, the selected regulated voltage value is unaltered by the feedback circuit, and wherein if the control signal indicates the clock signal is to be stopped, the feedback circuit reduces the selected regulated voltage value.

11. The circuit of claim 9, wherein the range comprises a lowest regulated voltage value and a highest regulated voltage value.

12. The circuit of claim 9, wherein the feedback circuit is configured to operate in response to the control signal.

13. The circuit of claim 8, wherein the transistor is configured to provide an electrical connection between the terminal and the other terminal in response to the control signal.

14. The circuit of claim 8, wherein the voltage regulator further comprises:

a voltage selection terminal configured to receive a selection input to select the selected regulated voltage value.

15. A method comprising:

regulating a selected voltage value at an output terminal by using a circuit including a voltage regulator coupled to the output terminal and a feedback circuit coupled to a feedback terminal of the voltage regulator and to the output terminal;

if a control signal to the feedback circuit does not indicate a clock signal is to be stopped, maintaining the selected voltage value in manner that is unaltered by the feedback circuit; and

if the control signal to the feedback circuit indicates the clock signal is to be stopped, reducing the selected voltage value by using the feedback circuit.

16. The method of claim 15, wherein the voltage regulator is configured to provide a range of voltage values.

17. The method of claim 16, further comprising:

coupling the feedback circuit to a voltage source with a voltage source value that is greater than the selected voltage value.

18. The method of claim 17, wherein the feedback circuit comprises:

a first resistor including a first terminal coupled to the output terminal and a second terminal coupled to the feedback terminal;

a second resistor including a third terminal and a fourth terminal that is coupled to the feedback terminal and to the second terminal; and

a transistor including a control terminal configured to receive the control signal, a terminal coupled to the third terminal, and another terminal configured to couple to the voltage source.

19. The method of claim 18, wherein the transistor is configured to provide an electrical connection between the terminal and the other terminal in response to the control signal.

20. The method of claim 15, wherein said regulating a selected voltage value comprises:

selecting the selected voltage value from a range of voltage values by using a voltage selection terminal of the voltage regulator.