Method and system for automatically generating executable system-level tests

• US 9,690,681 B1
• Filed: 09/03/2015
• Issued: 06/27/2017
• Est. Priority Date: 09/03/2015
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Ovadia, Meir, Singer, Erez, Gavish, Efrat
• Primary Examiner(s): Butler, Sarai
• Application Number:
  US14/844,529
• Time in Patent Office: 663 Days
• Field of Search: 714 33
• CPC Class Codes: G06F 11/2242 in multi-processor systems, e.g. one processor becoming the test master G06F11/2736 takes precedence
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
• CPC Class Codes: G06F 12/023 Free address space management

Abstract

A method for automatically generating executable system-level tests may include receiving scenario information for testing a device under test (DUT). The method may also include analyzing the scenario information to determine whether there is a legal order in which some or all actions included in the test are to be executed by a plurality of processors of the DUT requiring that one or a plurality of the actions be performed before one or a plurality of other actions may be performed; and identify necessary communications between the processors relating to synchronization points between them. The method may further include automatically generating a test that includes a plurality of actions performed by some or all of the processors in compliance with the legal order.

Claims

1. A method, comprising:

receiving scenario information for testing a device under test (DUT);

analyzing the scenario information to;

determine whether there is a legal order in which some or all actions to be executed by a plurality of processors of the DUT requiring that one or a plurality of said actions be performed before one or a plurality of other of said actions may be performed;

identify necessary communications between the plurality of processors relating to synchronization points between the plurality of processors of the DUT, and determine a minimal number of mail boxes for facilitating the communication between one or more pairs of processors from said plurality of processors; and

automatically generating a test by allocating the minimum number of mail boxes between the one or more pairs of processors from said plurality of processors, wherein the generated test includes a plurality of actions of said one or a plurality of actions performed by some or all of the plurality of processors in compliance with the legal order.

2. The method of claim 1, wherein the scenario information comprises a list of actions the user wishes to include in the test;

a list of processors and actions from said one or a plurality of actions that these processors are configured to execute;

inputs required by each processor for each action it may execute;

outputs of each of said processors pertaining to each action of said one or a plurality of actions that processor may execute; and

assignment of a communication protocol for communications between one or a plurality of pairs of said processors.

3. The method of claim 2, wherein the communication protocol assigned for communications between a first processor of said one or a plurality of pairs of processors and a second processor of said one or a plurality of pairs of processors is different from a communication protocol assigned for communications between the second processor and the first processor.

4. The method of claim 2, wherein the communication protocol comprises an address in memory and a size for mail boxes for the allotted memory.

5. The method of claim 1, further comprising adding to the generated test code to write to the allotted memory a unique identifier associated with a preceding action of said one or a plurality of actions after that action was executed.

6. The method of claim 5, further comprising adding to the generated test code to read from the allotted memory the unique identifier associated with the preceding action before a latter action of said one or a plurality of actions is to be executed.

7. A non-transitory computer readable storage medium having stored thereon instructions that when executed by a processor will cause the processor to:

receive scenario information for testing a device under test (DUT);

analyze the scenario information to;

determine whether there is a legal order in which some or all actions to be executed by a plurality of processors of the DUT requiring that one or a plurality of said actions be performed before one or a plurality of other of said actions may be performed; and

identify necessary communications between the plurality of processors relating to synchronization points between the plurality of processors of the DUT, and determine a minimal number of mail boxes for facilitating the communication between one or more pairs of processors from said plurality of processors; and

automatically generate a test by allocating the minimum number of mail boxes between the one or more pairs of processors from said plurality of processors, wherein the generated test includes a plurality of actions of said one or a plurality of actions performed by some or all of the plurality of processors in compliance with the legal order.

8. The non-transitory computer readable storage medium of claim 7, wherein the scenario information comprises a list of actions the user wishes to include in the test;

a list of processors and actions from said one or a plurality of actions that these processors are configured to execute;

inputs required by each processor for each action it may execute;

outputs of each of said processors pertaining to each action of said one or a plurality of actions that processor may execute; and

assignment of a communication protocol for communications between one or a plurality of pairs of said processors.

9. The non-transitory computer readable storage medium of claim 8, wherein the communication protocol comprises an address in memory and a size for mail boxes for the allotted memory.

10. The non-transitory computer readable storage medium of claim 7, further comprising adding to the generated test code to write to the allotted memory a unique identifier associated with a preceding action of said one or a plurality of actions after that action was executed.

11. The non-transitory computer readable storage medium of claim 10, having stored thereon instructions that when executed by a processor will cause the processor to further add to the generated test code to read from the allotted memory the unique identifier associated with the preceding action before a latter action of said one or a plurality of actions is to be executed.

12. A system, comprising:

a memory and

a processor configured to;

receive scenario information for testing a device under test (DUT);

analyze the scenario information to;

determine whether there is a legal order in which some or all actions to be executed by a plurality of processors of the DUT requiring that one or a plurality of said actions be performed before one or a plurality of other of said actions may be performed; and

identify necessary communications between the plurality of processors relating to synchronization points between the plurality of processors of the DUT, and determine a minimal number of mail boxes for facilitating the communication between one or more pairs of processors from said plurality of processors; and

automatically generate a test by allocating the minimum number of mail boxes between the one or more pairs of processors from said plurality of processors, wherein the generated test includes a plurality of actions of said one or a plurality of actions performed by some or all of the plurality of processors in compliance with the legal order.

13. The system of claim 12, wherein the scenario information comprises a list of actions the user wishes to include in the test;

a list of processors and actions from said one or a plurality of actions that these processors are configured to execute;

inputs required by each processor for each action it may execute;

outputs of each of said processors pertaining to each action of said one or a plurality of actions that processor may execute; and

assignment of a communication protocol for communications between one or a plurality of pairs of said processors.

14. The system of claim 13, wherein the communication protocol assigned for communications between a first processor of said one or a plurality of pairs of processors and a second processor of said one or a plurality of pairs of processors is different from a communication protocol assigned for communications between the second processor and the first processor.

15. The system of claim 14, wherein the communication protocol comprises an address in memory and a size for mail boxes for the allotted memory.

16. The system of claim 12, further comprising adding to the generated test code to write to the allotted memory a unique identifier associated with a preceding action of said one or a plurality of actions after that action was executed.

17. The system of claim 16, further comprising adding to the generated test code to read from the allotted memory the unique identifier associated with the preceding action before a latter action of said one or a plurality of actions is to be executed.