Camera control interface extension with in-band interrupt
First Claim
1. A method operational on a master device, comprising:
- controlling data transmissions over a bus coupling the master device and one or more slave devices, wherein data bits are transcoded into symbols for transmission across two lines of the bus and a clock signal is embedded within symbol transitions of the data transmissions; and
monitoring the bus during an interrupt period associated with transmission of a first signaling condition by the master device over a first line and a second line of the bus, wherein the one or more slave devices are enabled to assert an interrupt request using the first line of the bus in response to the transmission of the first signaling condition, andwherein the one or more slave devices are adapted to assert an interrupt request by pulling down the first line during the interrupt period.
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Accused Products
Abstract
Master and slave devices may be coupled to a control data bus. A method includes controlling data transmissions over a bus from a master device, where data bits are transcoded into symbols for transmission across two lines of the bus and a clock signal is embedded within symbol transitions of the data transmissions, and providing an interrupt period, during which one or more slave devices coupled to the bus can assert an interrupt request on a first line of the bus, within part of a heartbeat transmission by the master device over the first line and a second tine of the bus. The interrupt request may be an indicator that the asserting slave device wishes to request some action by the master device.
87 Citations
27 Claims
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1. A method operational on a master device, comprising:
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controlling data transmissions over a bus coupling the master device and one or more slave devices, wherein data bits are transcoded into symbols for transmission across two lines of the bus and a clock signal is embedded within symbol transitions of the data transmissions; and monitoring the bus during an interrupt period associated with transmission of a first signaling condition by the master device over a first line and a second line of the bus, wherein the one or more slave devices are enabled to assert an interrupt request using the first line of the bus in response to the transmission of the first signaling condition, and wherein the one or more slave devices are adapted to assert an interrupt request by pulling down the first line during the interrupt period. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A device, comprising:
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a bus including a first line and a second line; one or more slave devices coupled to the bus; and a master device coupled to the bus and controlling data transmissions between the master device and the one or more slave devices, wherein data bits are transcoded into symbols for transmission across the bus and a clock signal is embedded within symbol transitions of the data transmissions, wherein an interrupt period associated with transmission of a first signaling condition by the master device provides an opportunity for the one or more slave devices to assert an interrupt request on a first line of the bus, and wherein the master device is configured to monitor the first line for an interrupt request from a slave device during the interrupt period. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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19. A method operational on a slave device, comprising:
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receiving data transmissions over a bus from a master device, where data bits are transcoded into symbols for transmission across two lines of the bus, a clock signal is embedded within symbol transitions of the data transmissions, and an interrupt period is defined within the symbols received over the bus; and asserting an interrupt request on a first line of the bus while receiving a first signaling condition transmitted from the master device over the first line and a second line of the bus, wherein asserting the interrupt request includes pulling down the first line during the interrupt period. - View Dependent Claims (20, 21, 22, 23, 24, 25)
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26. A slave device, comprising:
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a bus interface for coupling to a first line and a second line; a processing circuit coupled to the bus interface and adapted to receive data transmissions over a bus from a master device, where data bits are transcoded into symbols for transmission across two lines of the bus, a clock signal is embedded within symbol transitions of the data transmissions, and an interrupt period is defined within the symbols received over the bus; assert an interrupt request using a first line of the bus while a first signaling condition is being transmitted by the master device over the first line and a second line of the bus; and internally mask the first line, during the interrupt period, for purposes of decoding the transcoded data bits received over the bus. - View Dependent Claims (27)
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Specification