System internal latency measurements in realtime applications

• US 9,690,727 B2
• Filed: 10/31/2014
• Issued: 06/27/2017
• Est. Priority Date: 10/31/2014
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Hanssen, Ingar, Courtel, Karl Jean-Paul, Birsan, Laurentiu, Danielsen, Stein
• Primary Examiner(s): SNYDER, STEVEN G
• Application Number:
  US14/530,622
• Publication Number:
  US 20160124879A1
• Time in Patent Office: 970 Days
• Field of Search: None
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 13/32 using combination of interrupt and burst mode transfer
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 15/7814 Specially adapted for real time processing, e.g. comprising hardware timers
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

Systems, methods, circuits and computer-readable mediums for system internal latency measurements in realtime applications are disclosed. In some implementations, a trigger signal is selected from a plurality of trigger signals for interrupting a processor of an integrated circuit system. The trigger signal includes a pulse having width. The system detects a rising edge of the pulse and starts a counter. The system detects a falling edge of the pulse and stops the counter. The system then compares a count of the counter with first and second values stored in first and second registers, respectively. The first value represents a minimum pulse width and the second value represents a maximum pulse width. The count is stored in the first or second register based on a result of the comparing.

Claims

1. A method comprising:

accessing a trigger signal from a plurality of trigger signals, the trigger signal including a pulse having a width;

detecting a rising edge of the pulse;

in response to the detecting of the rising edge, starting a counter;

detecting a falling edge of the pulse;

in response to the detecting of the falling edge;

stopping the counter;

comparing a count of the counter with first and second values stored in first and second registers, respectively, the first value representing a minimum pulse width and the second value representing a maximum pulse width;

storing the count in the first or second register based on a result of the comparing; and

dynamically adjusting a system clock frequency during runtime of an application based on the comparing.

2. The method of claim 1, where the trigger signal is an interrupt request signal from a peripheral of the integrated circuit system for interrupting at least one of a central processing unit (CPU), event system and a direct memory access (DMA) controller of the integrated circuit system.

3. The method of claim 1, further comprising:

transferring at least one of the first and second values to a buffer; and

determining a statistical distribution of time consumption based on the first and second values.

4. The method of claim 1, where comparing a count of the counter with first and second values stored in first and second registers, further comprises:

comparing the first value against the count to determine if the first value is greater than the count, and if the first value is greater than the count, storing the count in the first register as the minimum pulse width.

5. The method of claim 4, where comparing a count of the counter with first and second values stored in first and second registers, further comprises:

comparing the second value against the count to determine if the second value is less than the count and, if the second value is less than the count, storing the count in the second register as the maximum pulse width.

6. A system for performing system internal latency measurements, comprising:

a selecting device configured to select a trigger signal from a plurality of trigger signals, the trigger signal including a pulse having a width;

a counter coupled to the selecting device and configured to;

start counting when a rising edge of the pulse is detected and stop counting when a falling edge of the pulse is detected;

a compare and capture circuit coupled to the counter and configured to;

compare a count of the counter with first and second values stored in first and second registers, respectively, the first value representing a minimum pulse width and the second value representing a maximum pulse width; and

storing the count in the first or second register based on a result of the comparing; and

a processing unit or circuit configured to dynamically adjust a system clock frequency during runtime of an application based on the comparing.

7. The system of claim 6, where the trigger signal is an interrupt request signal from a peripheral of the integrated circuit system for interrupting at least one of a central processing unit (CPU), event system and a direct memory access (DMA) controller of the integrated circuit system.

8. The system of claim 6, further comprising:

an interface coupled to the first and second registers and configured to transfer at least one of the first and second values to a buffer; and

a central processing unit coupled to the interface and configured to determine a statistical distribution of time consumption based on the first and second values.

9. The system of claim 6, where comparing a count of the counter with first and second values stored in first and second registers, further comprises:

comparing the first value against the count to determine if the first value is greater than the count, and if the first value is greater than the count, storing the count in the first register as the minimum pulse width; and

comparing the second value against the count to determine if the second value is less than the count and, if the second value is less than the count, storing the count in the first register as the maximum pulse width.

10. The system of claim 6, where the system is included in a microcontroller system.

11. The system of claim 8, where the interface is a direct memory access (DMA) interface configured to perform a DMA transfer of the values to the buffer.

12. The system of claim 6, where the selecting device is a multiplexer.

13. The system of claim 6, where the first and second registers are initialized with maximum and minimum counter values, respectively.

14. The system of claim 13, further comprising a programmable register configured for storing the maximum counter value.

15. A non-transitory, computer-readable storage medium configured to store instructions, which, when executed by one or more processors, causes the one or more processors to perform operations comprising:

accessing a trigger signal from a plurality of trigger signals, the trigger signal including a pulse having a width;

detecting a rising edge of the pulse;

in response to the detecting of the rising edge, starting a counter;

detecting a falling edge of the pulse;

in response to the detecting of the falling edge;

stopping the counter;

comparing a count of the counter with first and second values stored in first and second registers, respectively, the first value representing a minimum pulse width and the second value representing a maximum pulse width;

storing the count in the first or second register based on a result of the comparing; and

dynamically adjusting a system clock frequency during runtime of an application based on the comparing.

16. The computer-readable medium of claim 15, where the trigger signal is an interrupt request signal from a peripheral of the integrated circuit system for interrupting at least one of a central processing unit (CPU), event system and a direct memory access (DMA) controller of the integrated circuit system.

17. The computer-readable medium of claim 15, further comprising:

transferring at least one of the first and second values to a buffer; and

determining a statistical distribution of time consumption based on the first and second values.

18. The computer-readable medium of claim 15, where comparing a count of the counter with first and second values stored in first and second registers, further comprises:

comparing the first value against the count to determine if the first value is greater than the count, and if the first value is greater than the count, storing the count in the first register as the minimum pulse width.

19. The computer-readable medium of claim 18, where comparing a count of the counter with first and second values stored in first and second registers, further comprises:

comparing the second value against the count to determine if the second value is less than the count and, if the second value is less than the count, storing the count in the second register as the maximum pulse width.