Method of operating and apparatus of memristor arrays with diagonal lines interconnect between memristor cells
First Claim
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1. A method of operating a plurality of memristive cells coupled as a memristor array comprising:
- initializing a first select line; and
in parallel for a number of memristor cells in the first select line;
determining whether a level of conductance of the memristor cells in the first select line are within a tolerance of a reference conductance; and
in response to a determination that the level of conductance is not within the tolerance of the reference conductance, adjusting the level of conductance for the memristor cells in the first select line.
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Abstract
A method of operating a plurality of memristive cells coupled as a memristor array includes initializing a first select line, and, in parallel for a number of memristor cells in the first select line, determining whether a level of conductance of the memristor cells in the first select line are within a tolerance of a reference conductance, and, in response to a determination that the level of conductance is not within the tolerance of the reference conductance, adjusting the level of conductance for the memristor cells in the first select line.
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Citations
20 Claims
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1. A method of operating a plurality of memristive cells coupled as a memristor array comprising:
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initializing a first select line; and in parallel for a number of memristor cells in the first select line; determining whether a level of conductance of the memristor cells in the first select line are within a tolerance of a reference conductance; and in response to a determination that the level of conductance is not within the tolerance of the reference conductance, adjusting the level of conductance for the memristor cells in the first select line. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A memristor array comprising:
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a number of row lines; a number of column lines intersecting the row lines to form a number of junctions; a number of memristive cells coupled between the row lines and the column lines at the junctions; a number of first diagonal lines coupled between the memristive cells in a first direction; and a number of second diagonal lines coupled between the memristive cells in a second direction, wherein the first diagonal lines and the second diagonal lines each couple at least two memristive cells via diagonally run interconnects with respect to the row lines and the column lines, and wherein the memristive cells are trained via application of a voltage via the first and second diagonal lines. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16)
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17. A method of operating a memristor array, comprising:
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performing a read function on a plurality of memristor cells on a select line; sensing a conductance level of the plurality of memristor cells on the select line; determining whether the conductance level of the plurality of memristor cells on the select line are greater than a reference conductance by comparing the conductance level of the plurality of memristor cells on first select line to the reference conductance; in response to a determination that the conductance level of the plurality of memristor cells on the select line are greater than the reference conductance, modifying reset conditions of the plurality of memristor cells and performing a reset operation; and in response to a determination that the conductance level of the plurality of memristor cells on the select line are less than the reference conductance, modifying set conditions of the plurality of memristor cells and performing a set operation. - View Dependent Claims (18, 19, 20)
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Specification