Memory array with RAM and embedded ROM

• US 9,691,495 B2
• Filed: 07/30/2014
• Issued: 06/27/2017
• Est. Priority Date: 07/30/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Yang, Jianan, Remington, Scott I., Zhang, Shayan
• Primary Examiner(s): Sofocleous, Alexander
• Assistant Examiner(s): Siddique, Mushfique
• Application Number:
  US14/447,515
• Publication Number:
  US 20160035433A1
• Time in Patent Office: 1,063 Days
• Field of Search: 365 72
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 17/08 using semiconductor devices, e.g. bipolar elements G11C17/06, G11C17/14 take precedence

Abstract

A memory array with RAM and embedded ROM including multiple RAM cells, a ROM cell, and a ROM enable circuit. Each RAM cell has a RAM cell structure with a first and second power terminals and configured to operate as a RAM cell when the memory array is in a RAM mode. The ROM cell has the same RAM cell structure in which at least one transistor is modified to cause the ROM cell to have a predetermined logic state. The ROM enable circuit enables bit lines of the ROM cell to control supply voltages provided to the power terminals of the RAM cells so that they settle to predetermined logic states in a ROM mode. The modified transistor has a pseudo transistor structure having a modified substrate that operates as a resistance, such as a doping region in the substrate having the same polarity type as the substrate.

Claims

1. A memory array, comprising:

an upper supply bus developing a supply voltage level relative to a reference voltage level developed on a lower supply bus;

a first switched supply bus and a second switched supply bus;

a plurality of RAM cells, each having a RAM cell structure with a first power terminal and a second power terminal and configured to operate as a RAM cell when the memory array is in a RAM mode, wherein for each of said plurality of RAM cells, said first power terminal is coupled to one of said first and second switched supply buses and wherein said second power terminal is coupled to the other one of said first and second switched supply buses;

a ROM cell comprising said RAM cell structure with first and second power terminals coupled to said upper supply bus, said ROM cell having at least one transistor that is modified so that said ROM cell settles to a predetermined logic state in either one of said RAM mode or a ROM mode, wherein said predetermined logic state is the same logic state in either one of said RAM mode and said ROM mode;

a RAM enable circuit that couples said first and second switched supply buses to said upper supply bus in said RAM mode, and that does not couple said first and second switched supply buses to said upper supply bus in said ROM mode; and

a ROM enable circuit that enables first and second bit lines of said ROM cell to couple only one of said first and second switched supply buses to said upper supply bus in said ROM mode so that each of said plurality of RAM cells operates as a ROM memory cell by settling to a predetermined logic state when the memory array is in said ROM mode, wherein said predetermined logic state of each of said plurality of RAM cells depends upon said predetermined logic state of said ROM cell.

2. The memory array of claim 1, wherein:

said RAM cell structure comprises a 6-T SRAM architecture; and

wherein said ROM cell comprises said 6-T SRAM architecture in which each of at least one MOS transistor of said 6-T SRAM architecture has been replaced by a pseudo MOS transistor structure having a substrate that is configured to form a resistance between a drain terminal and a source terminal.

3. The memory array of claim 2, wherein a doping region is formed within said substrate in which said doping region and said substrate have a common conductivity type.

4. The memory array of claim 1, wherein said ROM enable circuit enables said ROM cell in said ROM mode to allow the other one of said first and second switched supply buses to float.

5. The memory array of claim 1, wherein said ROM enable circuit enables said ROM cell in said ROM mode to couple the other one of said first and second switched supply buses to said lower supply bus.

6. The memory array of claim 1, wherein:

said ROM enable circuit comprises;

a first transistor having current terminals coupled between said upper supply bus and said first switched supply bus and having a control terminal coupled to said first bit line of said read only memory cell; and

a second transistor having current terminals coupled between said upper supply bus and said second switched supply bus and having a control terminal coupled to said second bit line of said read only memory cell; and

wherein said read only memory cell comprises;

a third transistor having current terminals coupled between a non-inverted bit line terminal and said ROM enable circuit and having a control terminal receiving a mode control signal; and

a fourth transistor having current terminals coupled between an inverted bit line terminal and said ROM enable circuit and having a control terminal receiving said mode control signal.

7. The memory array of claim 1, wherein:

said ROM enable circuit comprises;

a first transistor having current terminals coupled between said upper supply bus and said first switched supply bus and having a control terminal coupled to said first bit line of said ROM cell; and

a second transistor having current terminals coupled between said lower supply bus and said second switched supply bus and having a control terminal coupled to said second bit line of said ROM cell; and

wherein said read only memory cell comprises;

a third transistor having current terminals coupled between a non-inverted bit line terminal and said ROM enable circuit and having a control terminal receiving a mode control signal; and

a fourth transistor having current terminals coupled between an inverted bit line terminal and said ROM enable circuit and having a control terminal receiving said mode control signal.

8. The memory array of claim 1,

wherein said ROM cell comprises:

a first PMOS transistor having current terminals coupled between said upper supply bus and a first bit node and having a gate terminal coupled to a second bit node; and

a pseudo PMOS transistor structure having current terminals coupled between said upper supply bus and said second bit node and having a gate terminal coupled to said first bit node.

9. The memory array of claim 1,

wherein said ROM cell comprises:

a first NMOS transistor having current terminals coupled between a first bit node and said lower supply bus and having a gate terminal coupled to a second bit node; and

a pseudo NMOS transistor structure having current terminals coupled between said second bit node and said lower supply bus and having a gate terminal coupled to said first bit node.

10. A memory system, comprising:

an upper supply bus and a lower supply bus;

a first switched supply bus and a second switched supply bus;

a RAM enable circuit that pulls said first switched supply bus and said second switched supply bus to a voltage of said upper supply bus when a RAM mode signal indicates a RAM mode, and that otherwise releases said first switched supply bus and said second switched supply bus;

a plurality of RAM cells, each having an SRAM cell structure operative as an SRAM memory cell in said RAM mode, and each including a first power terminal coupled to one of said first and second switched supply buses and having a second power terminal coupled to the other of said first and second switched supply buses;

a ROM cell comprising said SRAM cell structure coupled to said upper supply bus and said lower supply bus in which said SRAM cell structure of said ROM cell includes at least one transistor that is modified to transition said ROM cell to a predetermined logic state in either one of said RAM mode or said ROM mode, wherein said predetermined logic state is the same logic state in either one of said RAM mode and a ROM mode; and

a ROM enable circuit coupled between said ROM cell and said first and second switched supply buses, wherein said ROM enable circuit enables first and second bit lines of said ROM cell to pull only one of said first and second switched supply buses to said voltage of said upper supply bus in said ROM mode based on said predetermined logic state of said ROM cell in which each of said plurality of RAM cells operates as a ROM memory cell by settling to a predetermined logic state in said ROM mode, and wherein said predetermined logic state of each of said plurality of RAM cells depends upon said predetermined logic state of said ROM cell.

11. The memory system of claim 10, wherein:

said ROM cell comprises;

a first NMOS transistor having current terminals coupled between a first bit node and a first bit line and having a control terminal receiving a ROM mode signal indicative of said ROM mode; and

a second NMOS transistor having current terminals coupled between a second bit node and a second bit line and having a control terminal receiving said ROM mode signal; and

wherein said ROM enable circuit comprises;

a first PMOS transistor having current terminals coupled between said upper supply bus and said first switched supply bus and having a control terminal coupled to said first bit line; and

a second PMOS transistor having current terminals coupled between said upper supply bus and said second switched supply bus and having a control terminal coupled to said second bit line.

12. The memory system of claim 10, wherein:

said ROM cell comprises;

a first NMOS transistor having current terminals coupled between a first bit node and a first bit line and having a control terminal receiving a ROM mode signal indicative of said ROM mode; and

a second NMOS transistor having current terminals coupled between a second bit node and a second bit line and having a control terminal receiving said ROM mode signal; and

wherein said ROM enable circuit comprises;

a PMOS transistor having current terminals coupled between said upper supply bus and said first switched supply bus and having a control terminal coupled to said first bit line; and

a third NMOS transistor having current terminals coupled between said lower supply bus and said second switched supply bus and having a control terminal coupled to said second bit line.

13. The memory system of claim 10, wherein said plurality of RAM cells comprises:

a first RAM cell comprising a first power terminal coupled to said first switched supply bus and a second power terminal coupled to said second switched supply bus, wherein said first RAM cell settles to a first logic state during said ROM mode; and

a second RAM cell comprising a first power terminal coupled to said second switched supply bus and a second power terminal coupled to said first switched supply bus, wherein said second RAM cell settles to a second logic state during said ROM mode.

14. The memory system of claim 10, wherein said ROM cell comprises a pseudo MOS transistor structure having current terminals coupled between an internal bit node and one of said upper and lower supply buses.

15. The memory system of claim 14, wherein said pseudo MOS transistor structure comprises a pseudo PMOS transistor structure having current terminals coupled between said internal bit node and said upper supply bus.

16. The memory system of claim 14, wherein said pseudo MOS transistor structure comprises a pseudo NMOS transistor structure having current terminals coupled between said internal bit node and said lower supply bus.

17. A method of providing a memory array on a semiconductor substrate with RAM and embedded ROM, comprising:

forming an SRAM cell having an SRAM cell structure with a first power terminal coupled to a first switched supply node and with a second power terminal coupled to a second switched supply node;

providing a RAM enable circuit, responsive to a RAM mode input, that couples the first and second switched supply nodes to a supply voltage node in a RAM mode;

forming a ROM cell having the SRAM cell structure coupled to the supply voltage node, wherein said forming a ROM cell comprises forming the SRAM cell structure that is modified with at least one pseudo MOS transistor so that the ROM cell settles to a predetermined logic state in either the RAM mode or a ROM mode when powered, wherein the predetermined logic state is the same logic state in either one of the RAM mode and the ROM mode; and

forming a ROM enable circuit, responsive to a ROM mode input, that enables first and second bit lines of the ROM cell to couple only one of the first and second switched supply nodes to the supply voltage node in the ROM mode so that the SRAM cell operates as a ROM memory cell that settles to a predetermined logic state based on the predetermined logic state of the ROM cell.

18. The method of claim 17, wherein said forming a ROM enable circuit comprises enabling the first and second bit lines of the ROM cell to allow the other one of the first and second switched supply nodes to float in the ROM mode.

19. The method of claim 17, wherein said forming a ROM enable circuit comprises enabling the first and second bit lines of the ROM cell to couple the other one of the first and second switched supply nodes to a reference voltage node in the ROM mode.

20. The method of claim 17, wherein said forming at least one pseudo MOS transistor structure comprises doping a substrate to operate as a resistance between drain and source terminals.