Dynamic application of error correction code (ECC) based on error type

• US 9,691,505 B2
• Filed: 03/27/2015
• Issued: 06/27/2017
• Est. Priority Date: 03/27/2015
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Das, Debaleena, Agarwal, Rajat
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US14/670,412
• Publication Number:
  US 20160284424A1
• Time in Patent Office: 823 Days
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Error correction in a memory subsystem includes determining whether an error is a transient error or a persistent error, and adjusting an approach to ECC (error checking and correction) based on error type. The type of error can be determined by a built in self-test. If the error is a persistent error, the memory controller can perform in erasure mode, including correcting an erasure for an identified error location prior to applying an ECC correction algorithm. Otherwise, if the error is transient, the memory controller can perform standard full ECC correction by applying the ECC correction algorithm.

Claims

1. A method for error correction in a memory subsystem, comprising:

detecting, with ECC (error checking and correction) logic, an error in read data from a memory device during an access operation to a memory address of the memory device;

in response to detecting the error, executing a built in self-test (BIST) to determine if the error is a transient error at the memory address or a persistent error at the memory address; and

if the error is a persistent error, performing ECC in erasure mode, including correcting an erasure for the memory address prior to applying an ECC correction algorithm;

otherwise,

performing full ECC correction, including applying the ECC correction algorithm without erasures, treating the error as a random bit error.

2. The method of claim 1, wherein the memory device comprises a volatile memory device.

3. The method of claim 1, wherein the memory device comprises an in-package memory device.

4. The method of claim 1, wherein the memory device comprises a x4 DIMM (dual inline memory module).

5. The method of claim 1, wherein the memory device comprises a x8 DIMM (dual inline memory module).

6. The method of claim 1, wherein executing the BIST further comprises performing a loopback write test to the memory address.

7. The method of claim 6, wherein executing the BIST further comprises performing a single pattern write test.

8. The method of claim 6, wherein executing the BIST further comprises performing a single write test of a pattern that is an inverse of data that resulted in a non-zero syndrome.

9. The method of claim 1, wherein applying the ECC correction algorithm comprises performing a single device data correction (SDDC) routine.

10. A memory controller that performs error correction in a memory subsystem, comprising:

error checking and correction (ECC) logic to detect an error in data received from a memory device in response to a request to read a memory address of the memory device; and

I/O (input/output) hardware coupled to the memory device to send a signal to cause the memory device to perform a built in self-test (BIST) of the memory address to determine if the error is a transient error or a persistent error;

wherein the ECC logic is to perform ECC in erasure mode if the error is a persistent error, including to correct an erasure for the memory address prior to application of an ECC correction algorithm;

otherwise, the ECC logic is to perform full ECC correction, including application of the ECC correction algorithm without erasures, to treat the error as a random bit error.

11. The memory controller of claim 10, wherein the memory device is an in-package memory device packaged with the memory controller and a host processor in a system on a chip.

12. The memory controller of claim 10, wherein the memory device comprises a x8 DIMM (dual inline memory module).

13. The memory controller of claim 10, wherein the I/O hardware is to send a command to the memory device to cause the memory device to perform a loopback write test to the memory address.

14. The memory controller of claim 13, wherein the loopback write test comprises a single pattern write test.

15. The memory controller of claim 13, wherein the loopback write test comprises a single write test of a pattern that is an inverse of data that resulted in a non-zero syndrome.

16. The memory controller of claim 10, wherein the ECC logic is to perform single device data correction (SDDC) level correction.

17. An electronic device with a memory subsystem, comprising:

multiple DRAMs (dynamic random access memory devices) each including a memory array of separately addressable memory locations;

a memory controller including

error checking and correction (ECC) logic to detect an error in data received from a memory device in response to a request to read a memory address of the memory device; and

I/O (input/output) hardware coupled to the memory device to send a signal to cause the memory device to perform a built in self-test (BIST) of the memory address to determine if the error is a transient error or a persistent error;

wherein the ECC logic is to perform ECC in erasure mode if the error is a persistent error, including to correct an erasure for the memory address prior to application of an ECC correction algorithm;

otherwise, the ECC logic is to perform full ECC correction, including application of the ECC correction algorithm without erasures, to treat the error as a random bit error; and

a chassis system to couple the memory subsystem to a blade server.

18. The electronic device of claim 17, wherein the memory device comprises a x8 DIMM (dual inline memory module).

19. The electronic device of claim 17, wherein the memory controller I/O hardware is to send a command to the memory device to cause the memory device to perform a loopback write test to the memory address.

20. The electronic device of claim 17, wherein the ECC logic is to perform single device data correction (SDDC) level correction.