Package-on-package assembly with wire bonds to encapsulation surface

• US 9,691,731 B2
• Filed: 12/22/2015
• Issued: 06/27/2017
• Est. Priority Date: 05/03/2011
• Status: Active Grant

• Current Assignee: Tessera (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Sato, Hiroaki, Hashimoto, Kiyoaki, Haba, Belgacem, Sakuma, Kazuo, Wang, Wei-Shun, Mohammed, Ilyas, Kang, Teck-Gyu, Masuda, Norihito, Inetaro, Kurosawa, Kikuchi, Tomoyuki, Osborn, Philip R., Chau, Ellis
• Primary Examiner(s): COLEMAN, WILLIAM D
• Application Number:
  US14/979,053
• Publication Number:
  US 20160211237A1
• Time in Patent Office: 553 Days
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/1713 Square or rectangular array
• CPC Class Codes: H01L 2224/17179 Corner adaptations, i.e. disposition of the bump connectors at the corners of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/45155 Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48106 the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 : Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/48245 : the item being metallic
• CPC Class Codes: H01L 2224/48247 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48455 : Details of wedge bonds
• CPC Class Codes: H01L 2224/48464 : the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 2224/49105 : Connecting at different heights
• CPC Class Codes: H01L 2224/49171 : Fan-out arrangements
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73207 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73215 : Layer and wire connectors
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06565 : the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1052 : Wire or wire-like electrical connections
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/107 : Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB printed circuits H05K1/00
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/4952 : the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/043 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 27/14618 : Containers
• CPC Class Codes: H01L 27/14625 : Optical elements or arrangements associated with the device
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip
• CPC Class Codes: H01L 2924/19107 : off-chip wires

Abstract

A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby.

Claims

1. A microelectronic package comprising:

a substrate having a first region and a second region, the substrate having a first surface and a second surface remote from the first surface;

at least one microelectronic element overlying the first surface within the first region and having contacts at a surface thereof;

first electrically conductive elements exposed at at least one of the first surface and the second surface of the substrate within the second region, at least some of the first conductive elements being electrically connected to the at least one microelectronic element;

first wire bonds having bases joined to respective ones of the first conductive elements, and end surfaces remote from the substrate and remote from the bases, each first wire bond defining an edge surface extending between the base and the end surface thereof;

second wire bonds having bases joined to respective ones of the contacts of the microelectronic element, and end surfaces remote from the surface of the microelectronic element and remote from the bases, each second wire bond defining an edge surface extending between the base and the end surface thereof; and

a dielectric encapsulation layer extending from at least one of the first or second surfaces and filling spaces between the first wire bonds and between the second wire bonds such that the first wire bonds and the second wire bonds are separated from one another by the encapsulation layer, the encapsulation layer overlying at least the second region of the substrate, wherein unencapsulated portions of the first wire bonds and the second wire bonds are defined by at least portions of the end surfaces of the first wire bonds and the second wire bonds that are uncovered by the encapsulation layer.

2. The microelectronic package of claim 1, further comprising a plurality of second conductive elements each electrically coupled with a respective first electrically conductive element through the first wire bond joined to the respective first electrically conductive element.

3. The microelectronic package of claim 1, wherein the first surface of the substrate extends in first and second lateral directions, each lateral direction being transverse to a direction of a thickness of the substrate between the first and second surfaces, and the unencapsulated portion of at least one of the first wire bonds is displaced in at least one of the lateral directions from the first electrically conductive element to which the at least one of the first wire bonds is joined.

4. The microelectronic package of claim 1, wherein the first conductive elements are arranged in a first array of a first predetermined configuration, and wherein the unencapsulated portions of the first wire bonds are arranged in a second array of a second predetermined configuration that is different from the first predetermined configuration.

5. The microelectronic package of claim 1, wherein the dielectric encapsulation layer includes a major surface at a first distance from the first surface of the substrate and a recessed surface at a second distance from first surface of the substrate that is less than the first distance, and wherein the unencapsulated portion of at least one of the first wire bonds is uncovered by the dielectric encapsulation layer at the recessed surface.

6. The microelectronic package of claim 1, wherein the dielectric encapsulation layer includes a major surface at a first distance from the first surface of the substrate, and the end surface of at least one of the first wire bonds or at least one of the second wire bonds is spaced above the major surface at a second distance from the first surface of the substrate that is greater than the first distance.

7. The microelectronic package of claim 1, further comprising an oxidation protection layer contacting at least some of the unencapsulated portions of the first wire bonds and the second wire bonds.

8. A microelectronic assembly, including:

a first microelectronic package according to claim 1; and

a second microelectronic package including a substrate having a first surface and a second surface, a second microelectronic element mounted to the first surface, and contact pads exposed at the second surface and electrically connected to the second microelectronic element;

wherein the second microelectronic package is mounted to the first microelectronic package such that the second surface of the second microelectronic package overlies at least a portion of the surface of the dielectric encapsulation layer and such that at least some of the contact pads are electrically and mechanically connected to at least some of the unencapsulated portions of the first wire bonds.

9. A system comprising the microelectronic package of claim 1 and one or more other electronic components electrically connected to the microelectronic package.

10. The microelectronic package of claim 3, wherein the unencapsulated portion of the at least one of the first wire bonds overlies a major surface of the microelectronic element.

11. The microelectronic package of claim 4, wherein the first predetermined configuration is characterized by a first pitch and wherein the second configuration is characterized by a second pitch that is finer than the first pitch.

12. The microelectronic package of claim 6, wherein a portion of the edge surface of the at least one of the first wire bonds or the at least one of the second wire bonds is uncovered by the dielectric encapsulation layer.

13. The system of claim 9, further comprising a housing, the microelectronic package and the one or more other electronic components being assembled with the housing.

14. The microelectronic package of claim 12, wherein at least a portion of the edge surface of the at least one of the first wire bonds or the at least one of the second wire bonds is coated with solder.

15. A microelectronic package comprising:

a substrate having a first region and a second region, the substrate having a first surface and a second surface remote from the first surface;

at least one microelectronic element overlying the first surface within the first region and having contacts at a surface thereof;

first electrically conductive elements exposed at at least one of the first surface and the second surface of the substrate within the second region, at least some of the first conductive elements being electrically connected to the at least one microelectronic element;

first wire bonds having bases joined to respective ones of the first conductive elements, and end surfaces remote from the substrate and remote from the bases, each first wire bond defining an edge surface extending between the base and the end surface thereof; and

second wire bonds having bases joined to respective ones of the contacts of the microelectronic element, and end surfaces remote from the surface of the microelectronic element and remote from the bases, each second wire bond defining an edge surface extending between the base and the end surface thereof.

16. The microelectronic package of claim 15, further comprising a plurality of second conductive elements each electrically coupled with a respective first electrically conductive element through the first wire bond joined to the respective first electrically conductive element.

17. The microelectronic package of claim 15, wherein the first surface of the substrate extends in first and second lateral directions, each lateral direction being transverse to a direction of a thickness of the substrate between the first and second surfaces, and the end surface of at least one of the first wire bonds is displaced in at least one of the lateral directions from the first electrically conductive element to which the at least one of the first wire bonds is joined.

18. The microelectronic package of claim 15, wherein the first conductive elements are arranged in a first array of a first predetermined configuration, and wherein the end surfaces of the first wire bonds are arranged in a second array of a second predetermined configuration that is different from the first predetermined configuration.

19. The microelectronic package of claim 17, wherein the end surface of the at least one of the first wire bonds overlies a major surface of the microelectronic element.

20. The microelectronic package of claim 18, wherein the first predetermined configuration is characterized by a first pitch and wherein the second configuration is characterized by a second pitch that is finer than the first pitch.