Vertical resistor in 3D memory device with two-tier stack

• US 9,691,781 B1
• Filed: 12/04/2015
• Issued: 06/27/2017
• Est. Priority Date: 12/04/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Miwa, Toru, Funayama, Kota, Ogawa, Hiroyuki, Nishikawa, Masatoshi
• Primary Examiner(s): Wright, Tucker J
• Application Number:
  US14/959,169
• Publication Number:
  US 20170162592A1
• Time in Patent Office: 571 Days
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.

Claims

1. A semiconductor device, comprising:

a substrate;

a stack in a memory cell area of the substrate, the stack comprising a first tier and a second tier on the first tier, the first tier comprising a first set of alternating control gate layers and dielectric layers and the second tier comprising a second set of alternating control gate layers and dielectric layers, the stack comprising memory holes, each memory hole comprises a portion in the first tier and a portion in the second tier, and memory films extend along a wall of each memory hole;

a transistor formed on the substrate in a peripheral area, peripheral to the memory cell area, the transistor is in a circuit;

a first column in the peripheral area, the first column comprises polysilicon, a resistor in the circuit comprises the polysilicon in the first column, and the first column extends from a terminal of the transistor to a height of a top of the first tier, wherein a doping concentration of the first column varies radially relative to a central longitudinal axis of the resistor; and

a second column which extends from the height of the top of the first tier to a height of a top of the second tier, the second column is electrically connected to the first column.

2. The semiconductor device of claim 1, wherein:

the second column comprises a metal contact to the polysilicon.

3. The semiconductor device of claim 1, wherein:

at least a bottom portion of the second column comprises polysilicon; and

the resistor in the circuit comprises the polysilicon in the at least the bottom portion of the second column.

4. The semiconductor device of claim 1, wherein:

the second column comprises polysilicon; and

a doping concentration of the polysilicon in the second column is different than a doping concentration of the polysilicon in the first column by at least an order of magnitude.

5. The semiconductor device of claim 1, wherein:

the polysilicon in the first column comprise a core along a central vertical axis of the first column and a surrounding region which surrounds the core; and

the core is intrinsic and the surrounding region is doped.

6. The semiconductor device of claim 1, wherein:

a bottom of the resistor is in contact with an n or p type diffusion region of the transistor in the substrate.

7. The semiconductor device of claim 1, wherein:

a bottom of the resistor is in contact with a control gate of the transistor.

8. The semiconductor device of claim 1, further comprising:

an additional column in the peripheral area, the additional column extends from the terminal of the transistor on the substrate to the height of the top of the first tier, wherein the second column is electrically connected to the additional column.

9. The semiconductor device of claim 1, wherein:

the first column is tapered, becoming narrower at a bottom of the first column;

the second column is tapered, becoming narrower at a bottom of the second column; and

a top of the first column is wider than a bottom of the second column.

10. The semiconductor device of claim 1, wherein:

a top of the first column at the height of the top of the first tier comprises, in a dielectric layer, a widened region which is wider than a remaining portion of the first column; and

for each memory hole, a top of the portion in the first tier has, in the dielectric layer, a widened region which is wider than a remaining portion of each memory hole in the first tier.

11. The semiconductor device of claim 1, wherein:

the control gate layers comprise control gates for memory cells;

the memory films comprise a charge trapping layer and tunnel oxide for the memory cells; and

the memory cells are arranged in NAND strings in a three-dimensional structure.

12. The semiconductor device of claim 1, wherein:

the first column extends through a silicon nitride layer to the terminal of the transistor.

13. The semiconductor device of claim 1, wherein:

the doping concentration decreases when moving radially outward from the central longitudinal axis.

14. The semiconductor device of claim 1, wherein:

the doping concentration increases when moving radially outward from the central longitudinal axis.

15. The semiconductor device of claim 1, wherein:

the polysilicon in the first column comprise a core and a surrounding region which surrounds the core; and

the core is doped and the surrounding region is intrinsic.

16. The semiconductor device of claim 1, wherein:

the polysilicon in the first column comprise a core and a layer surrounding the core; and

the layer has a different doping concentration than the core.

17. The semiconductor device of claim 1, wherein:

the polysilicon in the first column comprise a core and first and second layers surrounding the core; and

the first layer, the second layer and the core have different doping concentrations.

18. A semiconductor device, comprising:

a substrate;

a transistor formed on the substrate, the transistor is in a circuit;

a polysilicon column which is a resistor in the circuit, the polysilicon column is tapered, becoming narrower at a bottom of the polysilicon column, the polysilicon column comprise a core along a central vertical axis of the polysilicon column and a layer which surrounds the core, and the layer has a different doping concentration than the core; and

a metal column which is above the polysilicon column, wherein a bottom of the polysilicon column contacts a terminal of the transistor, a bottom of the metal column is on a top of the polysilicon column, and the metal column is tapered, becoming narrower at a bottom of the metal column.

19. The semiconductor device of claim 18, further comprising:

a three-dimensional array of NAND strings on the substrate, wherein the polysilicon column and the metal column are peripheral to the three-dimensional array of NAND strings, and the circuit is for providing a voltage to the three-dimensional array of NAND strings.

20. The semiconductor device of claim 18, wherein:

a doping concentration in the polysilicon column varies radially relative to a central vertical axis of the polysilicon column.