Non-volatile memory device

• US 9,691,782 B1
• Filed: 12/22/2016
• Issued: 06/27/2017
• Est. Priority Date: 04/29/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Ki-tae, Hwang, Chul-jin, Lim, Bong-soon
• Primary Examiner(s): Fourson, III, George
• Application Number:
  US15/388,369
• Time in Patent Office: 187 Days
• Field of Search: 257773, 257784, 257786
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A non-volatile memory device includes a substrate, a memory cell array on the substrate, a plurality of bonding pads, and a pad circuit. The memory cell array includes a plurality of gate conductive layers stacked on the substrate in a vertical direction and a plurality of channels penetrating into the plurality of gate conductive layers on an upper portion of the substrate. The plurality of bonding pads are on at least part of an upper portion of the memory cell array. The plurality of bonding pads are configured to electrically connect the non-volatile memory device to an external device. The pad circuit is between the substrate and the memory cell array. The pad circuit is electrically connected to at least one of the plurality of bonding pads.

Claims

1. A non-volatile memory device comprising:

a substrate;

a memory cell array on the substrate, the memory cell array including a plurality of gate conductive layers stacked on the substrate in a vertical direction and a plurality of channels penetrating into the plurality of gate conductive layers on an upper portion of the substrate;

a plurality of bonding pads on at least part of an upper portion of the memory cell array, the plurality of bonding pads being configured to electrically connect the non-volatile memory device to an external device; and

a pad circuit between the substrate and the memory cell array, the pad circuit being electrically connected to at least one of the plurality of bonding pads.

2. The non-volatile memory device according to claim 1, wherein the plurality of bonding pads are on at least part of an upper portion of an edge region of the memory cell array in which the channels are not disposed.

3. The non-volatile memory device according to claim 1, wherein the plurality of bonding pads are on at least part of an upper portion of a region of the memory cell array in which at least one dummy channel hole is disposed.

4. The non-volatile memory device according to claim 1, further comprising:

a peripheral circuit configured to write or read data to or from the memory cell array,

wherein the peripheral circuit is between the substrate and the memory cell array.

5. The non-volatile memory device according to claim 4, wherein the peripheral circuit is on the substrate and adjacent to the pad circuit in a horizontal direction.

6. The non-volatile memory device according to claim 4, wherein the pad circuit includes a data input/output circuit electrically connected between at least one of the plurality of bonding pads and the peripheral circuit.

7. The non-volatile memory device according to claim 4, wherein the pad circuit includes an electrostatic discharge (ESD) circuit electrically connected between at least one of the plurality of bonding pads and the peripheral circuit.

8. The non-volatile memory device according to claim 4, wherein the pad circuit includes a pull-up/pull-down circuit electrically connected between at least one of the plurality of bonding pads and the peripheral circuit.

9. The non-volatile memory device according to claim 1, wherein the pad circuit is on a lower portion of a side surface of the memory cell array adjacent to the plurality of bonding pads.

10. A non-volatile memory device comprising:

a substrate;

a first memory cell array on an upper portion of the substrate;

a second memory cell array on the upper portion of the substrate and adjacent to the first memory cell array;

a plurality of bonding pads on at least part of an upper portion of at least one of the first memory cell array and the second memory cell array, the plurality of bonding pads being configured to electrically connect the non-volatile memory device to an external device;

a first pad circuit between the substrate and the first memory cell array;

a second pad circuit between the substrate and the second memory cell array; and

a plurality of connection pads electrically connecting at least one of the first pad circuit and the second pad circuit to at least one of the plurality of bonding pads, at least one of the plurality of connection pads being on at least a part of the first memory cell array and a part of the second memory cell array.

11. The non-volatile memory device according to claim 10, wherein the first memory cell array and the second memory cell array are cell arrays having a vertical stack structure extending in the vertical direction with respect to the substrate.

12. The non-volatile memory device according to claim 10, wherein at least one of the plurality of connection pads is on at least part of the upper portion of at least one of the first memory cell array and the second memory cell array, between the first memory cell array and the second memory cell array.

13. The non-volatile memory device according to claim 10, wherein

the first pad circuit is on a lower portion of a side surface of the first memory cell array adjacent to the plurality of connection pads, and

the second pad circuit is on a lower portion of a side surface of the second memory cell array adjacent to the plurality of connection pads.

14. The non-volatile memory device according to claim 10, further comprising:

a peripheral circuit configured to write or read data to or from at least one of the first memory cell array and the second memory cell array, wherein

the peripheral circuit is adjacent to at least one of the first pad circuit and the second pad circuit in a horizontal direction.

15. The non-volatile memory device according to claim 14, wherein the first pad circuit and the second pad circuit each include one of an ESD circuit, a pull-up/pull-down driver, and a data input/output circuit that is electrically connected between the connection pads and the peripheral circuit.

16. A non-volatile memory device comprising:

a substrate;

a memory cell array on the substrate, the memory cell array including a plurality of gate conductive layers stacked on top of each other on a semiconductor layer and a plurality of channels penetrating the plurality of gate conductive layers towards the semiconductor layer in a vertical direction;

a plurality of bonding pads on the substrate over at least part of an upper portion of the memory cell array; and

a pad circuit between the substrate and the memory cell array, the pad circuit being electrically connected to at least one of the plurality of bonding pads.

17. The nonvolatile memory device of claim 16, further comprising:

an insulating thin film between the memory cell array and the substrate; and

a bonding pad contact, wherein

the insulating thin film defines an opening, and

the bonding pad contact extends through the opening to connect one of the at least one of the plurality of bonding pads to the pad circuit.

18. The nonvolatile memory device of claim 17, further comprising:

a common source line extending through the memory cell array in the vertical direction, wherein

the common source line is between the plurality of channels and the bonding pad contact, and

the bonding pad contact is spaced apart from the plurality of gate conductive layers.

19. The nonvolatile memory device of claim 16, further comprising:

a peripheral circuit between the substrate and the memory cell array, wherein

the peripheral circuit is adjacent to the pad circuit.

20. The nonvolatile memory device of claim 16, wherein the plurality of bonding pads are over an edge region of the memory cell array in which the channels are not disposed.