Semiconductor device and manufacturing method thereof

• US 9,691,851 B1
• Filed: 06/10/2016
• Issued: 06/27/2017
• Est. Priority Date: 06/10/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Fung, Ka-Hing
• Primary Examiner(s): Tobergte, Nicholas
• Application Number:
  US15/179,008
• Time in Patent Office: 382 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0684 characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66469 with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device includes one nanowire structure disposed on semiconductor substrate and extending in first direction on semiconductor substrate. Each nanowire structure includes plurality of nanowires extending along first direction and arranged in second direction, the second direction being substantially perpendicular to first direction. Each nanowire is spaced-apart from immediately adjacent nanowire. A gate structure extends in third direction over first region of nanowire structure, the third direction being substantially perpendicular to both first direction and second direction. The gate structure includes a gate electrode. Source/drain regions are disposed over second region of nanowire structure, the second region being located on opposing sides of gate structure. The gate electrode wraps around each nanowire. When viewed in cross section taken along third direction, each nanowire in nanowire structure is differently shaped from other nanowires, and each nanowire has substantially same cross-sectional area as other nanowires in nanowire structure.

Claims

1. A semiconductor device, comprising:

at least one nanowire structure disposed on a semiconductor substrate and extending in a first direction on the semiconductor substrate,

wherein each nanowire structure comprises a plurality of nanowires extending along the first direction and arranged in a second direction, the second direction being substantially perpendicular to the first direction,

wherein each nanowire is spaced-apart from an immediately adjacent nanowire;

a gate structure extending in a third direction over a first region of the nanowire structure, the third direction being substantially perpendicular to both the first direction and the second direction, and the gate structure including a gate electrode;

source/drain regions disposed over a second region of the nanowire structure, the second region of the nanowire structure being located on opposing sides of the gate structure,

wherein the gate electrode wraps around each of the nanowires, and

when viewed in a cross section taken along the third direction each nanowire in the nanowire structure is differently shaped from other nanowires in the nanowire structure, and each nanowire in the nanowire structure has a substantially same cross-sectional area as other nanowires in the nanowire structure.

2. The semiconductor device of claim 1, wherein the nanowire located furthest from the substrate is substantially trapezoidal-shaped when viewed in the cross section.

3. The semiconductor device of claim 1, wherein the nanowire located closest to the substrate is substantially rectangular-shaped when viewed in the cross section.

4. The semiconductor device of claim 1, wherein when viewed in the cross section a first nanowire located further from the substrate than an adjacent second nanowire has a longer length extending in the second direction than the second nanowire.

5. The semiconductor device of claim 1, wherein when viewed in the cross section a first nanowire located further from the substrate than an adjacent second nanowire has a shorter width extending in the third direction than the second nanowire.

6. The semiconductor device of claim 1, wherein immediately adjacent nanowires in the nanowire structure are spaced-apart by a substantially equal distance.

7. The semiconductor device of claim 1, wherein the nanowires comprise SiGe.

8. The semiconductor device of claim 1, wherein the source/drain regions wrap around the nanowires.

9. A semiconductor device, comprising:

at least one nanowire structure disposed on a semiconductor substrate and extending in a first direction on the semiconductor substrate,

wherein each nanowire structure comprises a plurality of nanowires extending along the first direction and arranged in a second direction, the second direction being substantially perpendicular to the first direction,

wherein each nanowire is spaced-apart from other adjacent nanowires;

a gate structure extending in a third direction over a first region of the nanowire structure, the third direction being substantially perpendicular to both the first direction and the second direction, and the gate structure including a gate electrode;

source/drain regions disposed over a second region of the nanowire structure, the second region of the nanowire structure being located on opposing sides of the gate structure,

wherein the gate electrode wraps around each of the nanowires, and

when viewed in a cross section taken along the third direction a first nanowire located further from the substrate than an adjacent second nanowire has a longer length extending in the second direction than the second nanowire, and the first nanowire has a shorter width extending in the third direction than the second nanowire.

10. The semiconductor device of claim 9, wherein a nanowire located furthest from the substrate is substantially trapezoidal-shaped when viewed in the cross section.

11. The semiconductor device of claim 9, wherein a nanowire located closest to the substrate is substantially rectangular-shaped when viewed in the cross section.

12. The semiconductor device of claim 9, wherein immediately adjacent nanowires in the nanowire structure are spaced-apart by a substantially equal distance.

13. The semiconductor device of claim 9, wherein the source/drain regions wrap around the nanowires.

14. A semiconductor device, comprising:

at least one nanowire structure disposed on a semiconductor substrate and extending in a first direction on the semiconductor substrate,

wherein each nanowire structure comprises a plurality of nanowires extending along the first direction and arranged in a second direction, the second direction being substantially perpendicular to the first direction,

wherein each nanowire is spaced-apart from an immediately adjacent nanowire, and

wherein the nanowires comprise a first semiconductor material;

a layer of a second semiconductor material having a different lattice constant than the first semiconductor material between immediately adjacent nanowires in the nanowire structure; and

a gate structure extending in a third direction over a first region of the nanowire structure, the third direction being substantially perpendicular to both the first direction and the second direction, and the gate structure including a gate electrode,

wherein when viewed in a cross section taken along the third direction the nanowires comprise four sides, and the gate electrode wraps around at least portions of each of the four sides of the nanowires, and

wherein each nanowire in the nanowire structure is differently shaped from other nanowires in the nanowire structure.

15. The semiconductor device according to claim 14, wherein each nanowire in the nanowire structure has a substantially same cross-sectional area as other nanowires in the nanowire structure.

16. The semiconductor device according to claim 14, further comprising source/drain regions disposed over a second region of the nanowire structure, the second region of the nanowire structure being located on opposing sides of the gate structure,

wherein when viewed in the cross section taken along the third direction the source/drain regions wrap around at least portions of each of the four sides of the nanowires.

17. The semiconductor device according to claim 14, wherein the nanowire located furthest from the substrate is substantially trapezoidal-shaped when viewed in the cross section.

18. The semiconductor device of claim 14, wherein the nanowire located closest to the substrate is substantially rectangular-shaped when viewed in the cross section.

19. The semiconductor device of claim 14, wherein when viewed in the cross section a first nanowire located further from the substrate than an adjacent second nanowire has a longer length extending in the second direction than the second nanowire.

20. The semiconductor device of claim 14, wherein when viewed in the cross section a first nanowire located further from the substrate than an adjacent second nanowire has a shorter width extending in the third direction than the second nanowire.