Semiconductor devices and structures

• US 9,691,869 B2
• Filed: 10/11/2015
• Issued: 06/27/2017
• Est. Priority Date: 04/09/2012
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Cronquist, Brian, Or-Bach, Zvi, Sekar, Deepak C.
• Primary Examiner(s): Blum, David S
• Application Number:
  US14/880,276
• Publication Number:
  US 20160035722A1
• Time in Patent Office: 625 Days
• Field of Search: 257369, 257499
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/80011 Chemical cleaning, e.g. etching, flux
• CPC Class Codes: H01L 2224/80012 Mechanical cleaning, e.g. abrasion using hydro blasting, brushes, ultrasonic cleaning, dry ice blasting, gas-flow
• CPC Class Codes: H01L 2224/80013 Plasma cleaning
• CPC Class Codes: H01L 2224/8013 using marks formed on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/80132 using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/08 of an individual bonding area
• CPC Class Codes: H01L 24/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 : the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 : including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/12 : the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 : combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42384 : for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/456 : on silicon
• CPC Class Codes: H01L 29/66704 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66772 : Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78654 : Monocrystalline silicon transistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An Integrated Circuit device, including: a first layer including first transistors; and a second layer including second transistors overlaying the first layer, where the first transistors are facing down and the second transistors are facing up, and where the second layer includes a through layer via of less than 300 nm diameter.

Claims

1. An Integrated Circuit device, comprising:

a first layer comprising first transistors; and

a second layer comprising second transistors overlaying said first layer,

wherein said first transistors are facing down and said second transistors are facing up, and

wherein said second layer comprises a through layer via of less than 300 nm diameter, and

wherein said second transistors are aligned to said first transistors with a less than 40 nm alignment error.

2. An Integrated Circuit device according to claim 1,

wherein said second layer thickness is less than 2 microns.

3. An Integrated Circuit device according to claim 1,

wherein said second layer comprises a region of oxide isolation, and

wherein said oxide isolation has a leakage current of less than one picoamp per micron at a device power supply voltage of 1.5 and at 25°

C.

4. An Integrated Circuit device according to claim 1,

wherein at least one of said second transistors is a FinFET transistor.

5. An Integrated Circuit device according to claim 1,

wherein at least one of said second transistors is a fully depleted transistor.

6. An Integrated Circuit device according to claim 1,

wherein at least one of said second transistors is a high-k metal gate transistor.

7. An Integrated Circuit device, comprising:

a first layer comprising first transistors;

a second layer comprising second transistors overlaying said first layer; and

a first metal layer providing interconnection for said first transistors, said first metal layer is disposed either between said first layer and said second layer, or underneath said first layer,

wherein said first metal layer comprises mostly aluminum or copper,

wherein at least one of said second transistors is aligned to said first transistor with a less than 40 nm alignment error,

wherein said second layer comprises a region of high quality oxide isolation, and

wherein said oxide isolation has a leakage current of less than one picoamp per micron at a device power supply voltage of 1.5 and at 25°

C.

8. An Integrated Circuit device according to claim 7,

wherein said first transistors are facing down and said second transistors are facing up.

9. An Integrated Circuit device according to claim 7,

wherein said second layer thickness is less than 2 microns.

10. An Integrated Circuit device according to claim 7,

wherein said second layer comprises at least one through layer via of less than 300 nm diameter.

11. An Integrated Circuit device according to claim 7,

wherein at least one of said second transistors is a fully depleted transistor.

12. An Integrated Circuit device according to claim 7,

wherein at least one of said second transistors is a high-k metal gate transistor.

13. An Integrated Circuit device, comprising:

a first layer comprising first transistors;

a second layer comprising second transistors overlaying said first layer; and

a first metal layer providing interconnection for said first transistors, said first metal layer is disposed either between said first layer and said second layer or underneath said first layer,

wherein said first metal layer comprises mostly aluminum or copper,

wherein at least one of said second transistors is aligned to said first transistor with a less than 40 nm alignment error, and

wherein said second transistor comprises silicided contacts.

14. An Integrated Circuit device according to claim 13,

wherein said second layer comprises at least one through layer via of less than 300 nm diameter.

15. An Integrated Circuit device according to claim 13,

wherein said first transistors are facing down and said second transistors are facing up.

16. An Integrated Circuit device according to claim 13,

wherein at least one of said second transistors is a high-k metal gate transistor.

17. An Integrated Circuit device according to claim 13,

wherein at least one of said second transistors is a FinFET transistor.

18. An Integrated Circuit device according to claim 13,

wherein at least one of said second transistors is a fully depleted transistor.

19. An Integrated Circuit device according to claim 13,

wherein said second layer comprises a region of oxide isolation, and

wherein said oxide isolation has a leakage current of less than one picoamp per micron at a device power supply voltage of 1.5 and at 25°

C.