Germanium profile for channel strain

• US 9,691,898 B2
• Filed: 12/19/2013
• Issued: 06/27/2017
• Est. Priority Date: 12/19/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Sung, Hsueh-Chang, Lee, Tze-Liang, Li, Kun-Mu, Li, Chii-Horng, Kwok, Tsz-Mei
• Primary Examiner(s): Wilczewski, Mary
• Assistant Examiner(s): CHIU, TSZ K
• Application Number:
  US14/134,302
• Publication Number:
  US 20150179796A1
• Time in Patent Office: 1,286 Days
• Field of Search: 257282, 257369, 257E2106, 257E21675
• CPC Class Codes: H01L 21/02057 Cleaning during device manufacture
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

The present disclosure relates to a transistor device having a strained source/drain region comprising a strained inducing material having a discontinuous germanium concentration profile. In some embodiments, the transistor device has a gate structure disposed onto a semiconductor substrate. A source/drain region having a strain inducing material is disposed along a side of the gate structure within a source/drain recess in the semiconductor substrate. The strain inducing material has a discontinuous germanium concentration profile along a line extending from a bottom surface of the source/drain recess to a top surface of the source/drain recess. The discontinuous germanium concentration profile provides improved strain boosting and dislocation propagation.

Claims

1. A transistor device, comprising:

a gate structure disposed onto a semiconductor substrate;

strained source/drain regions arranged on opposing sides of the gate structure and comprising;

a first layer arranged along a bottom surface of a source/drain recess located within the semiconductor substrate and having a strain inducing component with a first concentration profile that decreases as a distance from the bottom surface increases; and

a second layer overlying the first layer and having the strain inducing component with a second concentration profile that is discontinuous with the first concentration profile of the first layer along a line extending from the bottom surface of the source/drain recess to a top of the source/drain recess, wherein the second concentration profile increases as a distance from the first layer increases.

2. The transistor device of claim 1, wherein the strained source/drain regions comprise:

a first silicon-germanium (SiGe) layer disposed onto the bottom surface of the source/drain recess and having a first germanium concentration profile that decreases as the distance from the bottom surface increases;

a second SiGe layer disposed onto the first SiGe layer, wherein the second SiGe layer has a second germanium concentration profile that is discontinuous with the first germanium concentration profile and that increases as a distance from the first SiGe layer increases; and

a third SiGe layer disposed onto the second SiGe layer, wherein the third SiGe layer has a constant third germanium concentration profile less than a maximum germanium concentration of the second SiGe layer.

3. The transistor device of claim 2, wherein the first SiGe layer has a different doping concentration profile along a first line extending normal to a first bottom surface comprising a <

100>

surface than along a second line extending normal to a second bottom surface comprising a <

111>

surface.

4. The transistor device of claim 2, wherein the first SiGe layer comprises a germanium concentration of approximately 40% along a lower surface of the first SiGe layer to a germanium concentration of approximately 10% along an upper surface of the first SiGe layer.

5. The transistor device of claim 2, wherein the second SiGe layer comprises a germanium concentration of approximately 30% along a lower surface of the second SiGe layer to a germanium concentration of approximately 70% along an upper surface of the first SiGe layer.

6. The transistor device of claim 2, wherein the third SiGe layer comprises a silicon cap layer comprising un-doped pure silicon.

7. The transistor device of claim 1, further comprising:

a first silicon-germanium (SiGe) layer disposed onto the bottom surface of the source/drain recess and having a first germanium concentration profile that decreases as the distance from the bottom surface increases; and

a second SiGe layer disposed onto the first SiGe layer, wherein the second SiGe layer has a second germanium concentration profile that is discontinuous with the first germanium concentration profile and that increases as a distance from the first SiGe layer increases.

8. The transistor device of claim 1, wherein the first SiGe layer vertically extends to a position that is laterally abuts the second SiGe layer.

9. The transistor device of claim 1, wherein the first concentration profile monotonically decreases from the bottom surface to a top surface of the first layer.

10. The transistor device of claim 1, wherein the first layer laterally contacts sidewalls of the second layer.

11. A transistor device, comprising:

a gate structure disposed on a semiconductor substrate;

a source/drain region disposed next to the gate structure in a source/drain recess within the semiconductor substrate and comprising a plurality of strain inducing silicon germanium (SiGe) layers that provide for a discontinuous germanium concentration profile along a line extending from a bottom surface of the source/drain recess to a top surface of the source/drain recess;

wherein one of the plurality of strain inducing SiGe layers abutting a bottom of the source/drain recess comprises a first germanium concentration profile that changes from a high germanium concentration at a first position to a lower germanium concentration at a second position overlying the first position; and

wherein the one of the plurality of strain inducing SiGe layers is separated from a gate dielectric layer of the gate structure by the semiconductor substrate along a vertical line perpendicular to an upper surface of the semiconductor substrate.

12. The transistor device of claim 11, wherein the plurality of strain inducing SiGe layers comprise:

a first silicon-germanium (SiGe) layer disposed onto the bottom surface of the source/drain recess and having a first germanium concentration profile;

a second SiGe layer disposed onto the first SiGe layer, wherein the second SiGe layer has a second germanium concentration profile that is discontinuous with the first germanium concentration profile; and

a third SiGe layer disposed onto the second SiGe layer, wherein the third SiGe layer has a third germanium concentration profile less than a maximum germanium concentration of the second SiGe layer.

13. The transistor device of claim 12, wherein the first SiGe layer has a different doping concentration profile along a first line extending normal to a first bottom surface comprising a <

100>

surface than along a second line extending normal to a second bottom surface comprising a <

111>

surface.

14. The transistor device of claim 11, wherein the source/drain recess has a sidewall comprising a first slanted surface with a positive slope connected to a second slanted surface with a negative slope, wherein the one of the plurality of strain inducing SiGe layers abuts the first slanted surface and the second slanted surface.

15. The transistor device of claim 11, further comprising:

a cap layer arranged over the plurality of strain inducing SiGe layers and having a planar upper surface that extends between the gate structure and a second gate structure.

16. A transistor device, comprising:

a gate structure disposed onto a semiconductor substrate; and

a first silicon germanium (SiGe) layer disposed within a recess in the semiconductor substrate and having a gradient first germanium concentration that decreases as a distance from a bottom of the recess increases;

a second SiGe layer disposed within the recess above the first SiGe layer and having a second germanium concentration that is discontinuous with the gradient first germanium concentration; and

a third SiGe layer arranged vertically over the second SiGe layer and laterally between the second SiGe layer and the gate structure, wherein the third SiGe layer has a third germanium concentration that is less than a maximum germanium concentration within the second SiGe layer.

17. The transistor device of claim 16, wherein the first SiGe layer is confined within the recess.

18. The transistor device of claim 16, wherein the second germanium concentration comprises a second gradient germanium concentration that increases as the distance from the bottom of the recess increases.

19. The transistor device of claim 16, wherein the first SiGe layer has a greater width than the second SiGe layer.

20. The transistor device of claim 16, wherein the first SiGe layer vertically extends to a position that is laterally abuts the second SiGe layer.