Semiconductor device and manufacturing method thereof

• US 9,691,903 B2
• Filed: 08/03/2016
• Issued: 06/27/2017
• Est. Priority Date: 07/07/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Chao-Hsuing, Chen, Hou-Yu, Lin, Chie-Iuan, Chao, Yuan-Shun, Li, Kuo Lung
• Primary Examiner(s): Tran, Long K
• Application Number:
  US15/227,134
• Publication Number:
  US 20170012128A1
• Time in Patent Office: 328 Days
• Field of Search: 257190, 257192
• CPC Class Codes: H01L 21/02123 the material containing silicon
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

In a method for manufacturing a semiconductor device, a fin structure including a first semiconductor layer, an oxide layer disposed over the first semiconductor layer and a second semiconductor layer disposed over the oxide layer is formed. An isolation insulating layer is formed so that the second semiconductor layer of the fin structure protrudes from the isolation insulating layer while the oxide layer and the first semiconductor layer are embedded in the isolation insulating layer. A third semiconductor layer is formed on the exposed second semiconductor layer so as to form a channel.

Claims

1. A semiconductor device, comprising:

a Fin FET device including;

a fin structure extending in a first direction and protruding from an isolation insulating layer, the fin structure including a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer; and

a gate stack including a gate electrode layer and a gate dielectric layer, covering a portion of the channel layer and extending in a second direction perpendicular to the first direction,

wherein a width of the well layer in the second direction at an interface between the well layer and the oxide layer is smaller than a width of the channel layer in the second direction.

2. The semiconductor device of claim 1, wherein the oxide layer includes SiGe oxide.

3. The semiconductor device of claim 2, wherein the oxide layer does not include a semiconductor SiGe.

4. The semiconductor device of claim 1, wherein the channel layer does not contain Ge.

5. The semiconductor device of claim 1, wherein the oxide layer is fully embedded in the isolation insulating layer.

6. The semiconductor device of claim 5, wherein a thickness of the oxide layers is in a range of 5 nm to 25 nm.

7. A semiconductor device, comprising:

a Fin FET device including;

a first fin structure and a second fin structure, both extending in a first direction and protruding from an isolation insulating layer, each of the first and second fin structures including a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer; and

a gate stack including a gate electrode layer and a gate dielectric layer, covering a portion of the channel layer of the first fin structure and a portion of the channel layer of the second fin structure, and extending in a second direction perpendicular to the first direction,

wherein a width of the well layer of the first fin structure in the second direction at an interface between the well layer of the first fin structure and the oxide layer of the first fin structure is smaller than a width of the channel layer of the first fin structure in the second direction.

8. The semiconductor device of claim 7, wherein the oxide layer includes SiGe oxide.

9. The semiconductor device of claim 8, wherein the oxide layer does not include a semiconductor SiGe.

10. The semiconductor device of claim 7, wherein the channel layer does not contain Ge.

11. The semiconductor device of claim 7, wherein the oxide layer is fully embedded in the isolation insulating layer.

12. The semiconductor device of claim 11, wherein a thickness of the oxide layers is in a range of 5 nm to 25 nm.

13. A semiconductor device, comprising:

a Fin FET device including;

a fin structure extending in a first direction and protruding from an isolation insulating layer, the fin structure including a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer; and

a gate stack including a gate electrode layer and a gate dielectric layer, covering a portion of the channel layer and extending in a second direction perpendicular to the first direction, wherein;

a bottom part of the channel layer is embedded in the isolation insulating layer, and

a width of the bottom part of the channel layer in the second direction is smaller than a largest width of the channel layer in the second direction.

14. The semiconductor device of claim 13, wherein the oxide layer includes SiGe oxide.

15. The semiconductor device of claim 14, wherein the oxide layer does not include a semiconductor SiGe.

16. The semiconductor device of claim 13, wherein the channel layer does not contain Ge.

17. The semiconductor device of claim 13, wherein the oxide layer is fully embedded in the isolation insulating layer.

18. The semiconductor device of claim 17, wherein a thickness of the oxide layers is in a range of 5 nm to 25 nm.

19. The semiconductor device of claim 13, wherein the channel layer has a portion in contact with an upper surface of the isolation insulating layer.

20. The semiconductor device of claim 13, wherein an oxide layer is disposed between a side surface of the channel layer and the isolation insulating layer.