Symmetric linear equalization circuit with increased gain

• US 9,692,381 B2
• Filed: 08/15/2016
• Issued: 06/27/2017
• Est. Priority Date: 05/16/2014
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Tajalli, Armin
• Primary Examiner(s): Nguyen, Khai M
• Application Number:
  US15/237,171
• Publication Number:
  US 20170040965A1
• Time in Patent Office: 316 Days
• Field of Search: 330252-254, 330260, 330292, 330302, 330304
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/26 Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• CPC Class Codes: H03F 1/32 Modifications of amplifiers to reduce non-linear distortion by negative feedback H03F1/34
• CPC Class Codes: H03F 1/3211 in differential amplifiers
• CPC Class Codes: H03F 1/565 using inductive elements
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/301 the loading circuit of an amplifying stage comprising a coil
• CPC Class Codes: H03F 2200/366 Multiple MOSFETs are coupled in parallel
• CPC Class Codes: H03F 2203/45022 One or more added resistors to the amplifying transistors in the differential amplifier
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45197 Pl types H03F3/45224, H03F3/45251 take precedence
• CPC Class Codes: H03G 1/0029 using FETs
• CPC Class Codes: H03G 3/3036 in high-frequency amplifiers or in frequency-changers H03G3/3052, H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03G 3/3089 Control of digital or coded signals

Abstract

Circuits providing low noise amplification with continuous time linear equalization are described. An exemplary circuit includes four amplification elements, such as MOS transistors. The amplification elements are arranged in differential pairs, and the differential pairs are cross-coupled with a frequency-dependent coupling, such as a capacitive coupling, to enhance high-frequency gain. The outputs of the amplification elements are combined to provide an output representing inverted and un-inverted sums of differences in the input signals.

Claims

1. An apparatus comprising:

a first amplification element comprising a first pair of complimentary MOS transistors, each of the first pair of complimentary MOS transistors having corresponding gate inputs and source inputs, the MOS transistors configured to receive a first signal representing a first symbol of a codeword at the corresponding gate inputs;

a second amplification element comprising a second pair of complimentary MOS transistors having corresponding gate inputs and source inputs, each of the second pair of complimentary MOS transistors configured to receive a second signal representing a second symbol of the codeword at the corresponding gate inputs;

a first frequency-dependent circuit configured to cross-couple the first input signal to the corresponding source inputs of the second pair of complimentary MOS transistors;

a second frequency-dependent circuit configured to cross-couple the second input signal to the corresponding source inputs of the first pair of complimentary MOS transistors; and

,

an impedance element connected to the first and second pairs of complimentary MOS transistors, the impedance element configured to generate an amplified codeword identification signal, the first and second amplification elements configured to provide a gain corresponding to a combination of common-source gain and common-gate gain, the common-source gain applied to the corresponding gate inputs of the first and second amplification elements and the common-gate gain applied to the frequency-dependent source inputs of the first and second amplification elements, the amplified codeword identification signal used at least in part to determine a set of output bits represented by the symbols of the codeword.

2. The apparatus of claim 1, wherein the symbols of the codeword have values selected from a set of at least three values.

3. The apparatus of claim 2, wherein the symbols of the codeword have values selected from the set {±

1, ±

⅓

}.

4. The apparatus of claim 3, wherein the codeword is a permutation of (+1, −

⅓

, −

⅓

, −

⅓

) and (−

1+⅓

, +⅓

, +⅓

).

5. The apparatus of claim 1, wherein the complimentary MOS transistors comprise serially-connected NMOS and PMOS transistors.

6. The apparatus of claim 1, wherein each pair of complementary MOS transistors comprises matched transistors.

7. The apparatus of claim 1, wherein the amplified codeword signal is a difference signal added to a second amplified codeword signal to form a sum-of-differences signal used in part in determining the set of output bits represented by the symbols of the codeword.

8. The apparatus of claim 7, wherein three sum-of-differences signals are used to determine the set of output bits.

9. The apparatus of claim 1, wherein the first and second frequency-dependent circuits are resistor-capacitor circuits.

10. The apparatus of claim 1, wherein the first and second frequency-dependent circuits are high-pass filters configured to inject high-frequency content of the first and second input signals into the source inputs of the second and first pairs of complementary MOS transistors, respectively.

11. A method comprising:

receiving a first signal representing a first symbol of a codeword at corresponding gate inputs of a first amplification element comprising a first pair of complimentary MOS transistors;

receiving a second signal representing a second symbol of the codeword at corresponding gate inputs of a second amplification element comprising a second pair of complimentary MOS transistors;

cross-coupling the first input signal using a first frequency-dependent circuit to corresponding source inputs of the second pair of complimentary MOS transistors;

cross-coupling the second input signal using a second frequency-dependent circuit to corresponding source inputs of the first pair of complimentary MOS transistors; and

,

generating an amplified codeword identification signal across an impedance element connected to the first and second pairs of complimentary MOS transistors, the first and second amplification elements providing a gain corresponding to a combination of common-source gain and common-gate gain, the common-source gain applied to the corresponding gate inputs of the first and second amplification elements and the common-gate gain applied to the frequency-dependent source inputs of the first and second amplification elements, the amplified codeword identification signal used at least in part to determine a set of output bits represented by the symbols of the codeword.

12. The method of claim 11, wherein the symbols of the codeword have values selected from a set of at least three values.

13. The method of claim 12, wherein the symbols of the codeword have values selected from the set {±

1, ±

⅓

}.

14. The method of claim 13, wherein the codeword is a permutation of (+1, −

⅓

, −

⅓

, −

⅓

) and (−

1+⅓

, +⅓

, +⅓

).

15. The method of claim 11, wherein the complimentary MOS transistors comprise serially-connected NMOS and PMOS transistors.

16. The method of claim 11, wherein each pair of complementary MOS transistors comprises matched transistors.

17. The method of claim 11, wherein the amplified codeword signal is a difference signal, and wherein the method further comprises adding the amplified codeword signal to a second amplified codeword signal to form a sum-of-differences signal used in part in determining the set of output bits represented by the symbols of the codeword.

18. The method of claim 17, wherein three sum-of-differences signals are used to determine the set of output bits.

19. The method of claim 11, wherein the first and second frequency-dependent circuits are resistor-capacitor circuits.

20. The method of claim 11, wherein cross-coupling the first and second input signals injects high-frequency content of the first and second input signals into the source inputs of the second and first pairs of complementary MOS transistors, respectively.