Ring oscillator architecture with controlled sensitivity to supply voltage

• US 9,692,396 B2
• Filed: 05/13/2015
• Issued: 06/27/2017
• Est. Priority Date: 05/13/2015
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Yu, Xinxin, Swaminathan, Ashok, Venerus, Christian
• Primary Examiner(s): Tan, Richard
• Application Number:
  US14/711,158
• Publication Number:
  US 20160336924A1
• Time in Patent Office: 776 Days
• Field of Search: 331 57, 331185, 327250, 327393, 327395, 327400
• CPC Class Codes: H03K 3/011 Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature to maintain energy constant H03K3/015
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/0997 Controlling the number of delay elements connected in series in the ring oscillator

Abstract

A method and apparatus for controlling a supply sensitivity of a ring oscillator stage are provided. The apparatus is configured to generate, via a voltage biasing module, a first bias signal for a PMOS biasing module based on a supply voltage and a second bias signal for a NMOS biasing module based on the supply voltage, bias, via the PMOS biasing module, triode PMOS degeneration of the inverting module based on the first bias signal, bias, via the NMOS biasing module, triode NMOS degeneration of the inverting module based on the second bias signal, receive an input via an inverting module, and output, via the inverting module, an inverted version of the received input based on the biased triode NMOS degeneration and the biased triode PMOS degeneration.

Claims

1. An apparatus for controlling a supply sensitivity of a ring oscillator stage, comprising:

an inverting module configured to output an inverted version of a received input;

a PMOS biasing module coupled to the inverting module and comprising at least one element having a tunable resistance based on a first bias signal;

an NMOS biasing module coupled to the inverting module and comprising at least one element having a tunable resistance based on a second bias signal; and

a voltage biasing module configured to generate the first bias signal for the PMOS biasing module based on a supply voltage and generate the second bias signal for the NMOS biasing module based on the supply voltage, the voltage biasing module comprising a first PMOS transistor, an NMOS transistor, a second PMOS transistor, and a current source, wherein a drain of the first PMOS transistor is coupled to a drain of the NMOS transistor and to the PMOS biasing module, wherein a gate of the NMOS transistor is coupled to the NMOS biasing module, and wherein a gate of the first PMOS transistor is coupled to a gate of the second PMOS transistor,

wherein a source of the first PMOS transistor is coupled to the supply voltage,

wherein a source of the second PMOS transistor is coupled to the supply voltage,

wherein a drain of the second PMOS transistor is coupled to a first node of the current source and the gate of the NMOS transistor and coupled to the gate of the second PMOS transistor,

wherein the PMOS biasing module biases the inverting module based on the first bias signal,

wherein the NMOS biasing module biases the inverting module based on the second bias signal, and

wherein the inverting module outputs the inverted version of the received input based on the NMOS biasing module bias and the PMOS biasing module bias.

2. The apparatus of claim 1, wherein the inverting module comprises:

a primary PMOS transistor; and

a primary NMOS transistor coupled to the primary PMOS transistor,

wherein a gate of the primary PMOS transistor and a gate of the primary NMOS transistor is coupled to an input of the ring oscillator stage, and

wherein a drain of the primary PMOS transistor and a drain of the primary NMOS transistor are coupled to an output of the ring oscillator stage.

3. The apparatus of claim 2, wherein the PMOS biasing module comprises a first secondary PMOS transistor, a second secondary PMOS transistor, a third secondary PMOS transistor, and a fourth secondary PMOS transistor,

wherein a source of the primary PMOS transistor is coupled to a drain of the first secondary PMOS transistor, a drain of the second secondary PMOS transistor, a drain of the third secondary PMOS transistor, and a drain of the fourth secondary PMOS transistor,

wherein a source of the first secondary PMOS transistor, a source of the second secondary PMOS transistor, a source of the third secondary PMOS transistor, and a source of the fourth secondary PMOS transistor is coupled to the supply voltage,

wherein a resistance of each of the first secondary PMOS transistor, the second secondary PMOS transistor, the third secondary PMOS transistor, and the fourth secondary PMOS transistor is controlled based on the supply voltage by respectively receiving the first bias signal from the voltage biasing module, and

wherein each of the first secondary PMOS transistor, the second secondary PMOS transistor, the third secondary PMOS transistor, and the fourth secondary PMOS transistor receives the first bias signal via a respective gate node.

4. The apparatus of claim 3, wherein the NMOS biasing module comprises a first secondary NMOS transistor, a second secondary NMOS transistor, a third secondary NMOS transistor, and a fourth secondary NMOS transistor,

wherein a source of the primary NMOS transistor is coupled to a drain of the first secondary NMOS transistor, a drain of the second secondary NMOS transistor, a drain of the third secondary NMOS transistor, and a drain of the fourth secondary NMOS transistor,

wherein a source of the first secondary NMOS transistor, a source of the second secondary NMOS transistor, a source of the third secondary NMOS transistor, and a source of the fourth secondary NMOS transistor is coupled to a ground node,

wherein a resistance of each of the first secondary NMOS transistor, the second secondary NMOS transistor, the third secondary NMOS transistor, and the fourth secondary NMOS transistor is controlled based on the supply voltage by respectively receiving the second bias signal from voltage biasing module, and

wherein each of the first secondary NMOS transistor, the second secondary NMOS transistor, the third secondary NMOS transistor, and the fourth secondary NMOS transistor receives the second bias signal via a respective gate node.

5. The apparatus of claim 4,

wherein the drain of the first PMOS transistor is coupled to the gate of the first secondary PMOS transistor, the gate of the second secondary PMOS transistor, the gate of the third secondary PMOS transistor, and the gate of the fourth secondary PMOS transistor.

6. The apparatus of claim 5,

wherein the drain of the NMOS transistor is coupled to the gate of the first secondary PMOS transistor, the gate of the second secondary PMOS transistor, the gate of the third secondary PMOS transistor, and the gate of the fourth secondary PMOS transistor,

wherein a source of the NMOS transistor is coupled to the ground node, and

wherein the gate of the NMOS transistor is coupled to the gate of the first secondary NMOS transistor, the gate of the second secondary NMOS transistor, the gate of the third secondary NMOS transistor, and the gate of the fourth secondary NMOS transistor.

7. The apparatus of claim 6,

wherein a second node of the current source is coupled to the ground node.

8. The apparatus of claim 1, wherein the supply sensitivity is based at least in part on the tuned resistance of the at least one element of the PMOS biasing module and the tuned resistance of the at least one element of the NMOS biasing module.

9. The apparatus of claim 1, wherein the at least one element of the PMOS biasing module and the at least one element of the NMOS biasing module provide degeneration for the inverting module.

10. The apparatus of claim 1, wherein the PMOS biasing module and the NMOS biasing module each comprise a plurality of elements having a tunable resistance, wherein each of the plurality of elements comprises a transistor in series with a switch.

11. The apparatus of claim 1, wherein a second node of the current source is coupled to a source of the NMOS transistor.

12. The apparatus of claim 11, wherein the source of the first PMOS transistor is further coupled to one or more switches in the PMOS biasing module, and wherein the source of the NMOS transistor is further coupled to one or more switches in the NMOS biasing module.

13. A method for controlling a supply sensitivity of a ring oscillator stage, comprising:

generating, via a voltage biasing module, a first bias signal for a PMOS biasing module based on a supply voltage and a second bias signal for an NMOS biasing module based on the supply voltage, the first bias signal being provided from a node to which a drain of an NMOS transistor and a drain of a first PMOS transistor in the voltage biasing module are coupled, the second biasing signal being provided from a node coupled to a gate of the NMOS transistor, wherein the drain of the first PMOS transistor is not connected to a gate of the first PMOS transistor,

wherein the voltage biasing module further comprises a second PMOS transistor and a current source;

a source of the first PMOS transistor is coupled to the supply voltage, and the gate of the first PMOS transistor is coupled to a gate of the second PMOS transistor,

wherein a source of the second PMOS transistor is coupled to the supply voltage, and

wherein a drain of the second PMOS transistor is coupled to a first node of the current source and the gate of the NMOS transistor and coupled to the gate of the second PMOS transistor,

tuning a resistance of at least one element of the PMOS biasing module based on the first bias signal;

tuning a resistance of at least one element of the NMOS biasing module based on the second bias signal;

biasing, via the PMOS biasing module, PMOS degeneration of an inverting module based on the tuned resistance of the at least one element of the PMOS biasing module;

biasing, via the NMOS biasing module, NMOS degeneration of the inverting module based on the tuned resistance of the at least one element of the NMOS biasing module;

receiving an input via the inverting module; and

outputting, via the inverting module, an inverted version of the received input based on the NMOS degeneration and the PMOS degeneration.

14. The method of claim 13, wherein the inverting module comprises:

a primary PMOS transistor; and

a primary NMOS transistor coupled to the primary PMOS transistor,

wherein a gate of the primary PMOS transistor and a gate of the primary NMOS transistor is coupled to an input of the ring oscillator stage, and

wherein a drain of the primary PMOS transistor and a drain of the primary NMOS transistor are coupled to an output of the ring oscillator stage.

15. The method of claim 14, wherein the PMOS biasing module comprises a first secondary PMOS transistor, a second secondary PMOS transistor, a third secondary PMOS transistor, and a fourth secondary PMOS transistor,

wherein a source of the primary PMOS transistor is coupled to a drain of the first secondary PMOS transistor, a drain of the second secondary PMOS transistor, a drain of the third secondary PMOS transistor, and a drain of the fourth secondary PMOS transistor,

wherein a source of the first secondary PMOS transistor, a source of the second secondary PMOS transistor, a source of the third secondary PMOS transistor, and a source of the fourth secondary PMOS transistor is coupled to the supply voltage,

wherein a resistance of each of the first secondary PMOS transistor, the second secondary PMOS transistor, the third secondary PMOS transistor, and the fourth secondary PMOS transistor is controlled based on the supply voltage by respectively receiving the first bias signal from the voltage biasing module, and

wherein each of the first secondary PMOS transistor, the second secondary PMOS transistor, the third secondary PMOS transistor, and the fourth secondary PMOS transistor receives the first bias signal via a respective gate node.

16. The method of claim 15, wherein the NMOS biasing module comprises a first secondary NMOS transistor, a second secondary NMOS transistor, a third secondary NMOS transistor, and a fourth secondary NMOS transistor,

wherein a source of the primary NMOS transistor is coupled to a drain of the first secondary NMOS transistor, a drain of the second secondary NMOS transistor, a drain of the third secondary NMOS transistor, and a drain of the fourth secondary NMOS transistor,

wherein a source of the first secondary NMOS transistor, a source of the second secondary NMOS transistor, a source of the third secondary NMOS transistor, and a source of the fourth secondary NMOS transistor is coupled to a ground node,

wherein a resistance of each of the first secondary NMOS transistor, the second secondary NMOS transistor, the third secondary NMOS transistor, and the fourth secondary NMOS transistor is controlled based on the supply voltage by respectively receiving the second bias signal from voltage biasing module, and

wherein each of the first secondary NMOS transistor, the second secondary NMOS transistor, the third secondary NMOS transistor, and the fourth secondary NMOS transistor receives the second bias signal via a respective gate node.

17. The method of claim 16,

wherein the drain of the first PMOS transistor is coupled to the gate of the first secondary PMOS transistor, the gate of the second secondary PMOS transistor, the gate of the third secondary PMOS transistor, and the gate of the fourth secondary PMOS transistor.

18. The method of claim 17,

wherein the drain of the NMOS transistor is coupled to the gate of the first secondary PMOS transistor, the gate of the second secondary PMOS transistor, the gate of the third secondary PMOS transistor, and the gate of the fourth secondary PMOS transistor,

wherein a source of the NMOS transistor is coupled to the ground node, and

wherein the gate of the NMOS transistor is coupled to the gate of the first secondary NMOS transistor, the gate of the second secondary NMOS transistor, the gate of the third secondary NMOS transistor, and the gate of the fourth secondary NMOS transistor.

19. The method of claim 18,

wherein a second node of the current source is coupled to the ground node.

20. An apparatus for controlling a supply sensitivity of a ring oscillator stage, comprising:

inverting means for receiving an input and outputting an inverted version of the received input;

PMOS biasing means for biasing PMOS degeneration of the inverting means, the PMOS biasing means comprising means for tuning a resistance of the PMOS biasing means based on a first bias signal;

NMOS biasing means for biasing NMOS degeneration of the inverting means, the NMOS biasing means comprising means for tuning a resistance of the NMOS biasing means based on a second bias signal; and

voltage biasing means for generating the first bias signal for the PMOS biasing means based on a supply voltage and the second bias signal for the NMOS biasing means based on the supply voltage, the voltage biasing means comprising a first PMOS transistor, an NMOS transistor, a second PMOS transistor and means for providing a current comprising a current source, wherein a drain of the first PMOS transistor is coupled to a drain of the NMOS transistor and to the PMOS biasing means, wherein a gate of the NMOS transistor is coupled to the NMOS biasing means, and wherein a source of the NMOS transistor is coupled to the means for providing current, and

wherein a source of the first PMOS transistor is coupled to the supply voltage and the gate of the first PMOS transistor is coupled to a gate of the second PMOS transistor,

wherein a source of the second PMOS transistor is coupled to the supply voltage,

wherein a drain of the second PMOS transistor is coupled to a first node of the current source and the gate of the NMOS transistor and coupled to the gate of the second PMOS transistor, and

wherein the inverted version of the received input is outputted via the inverting means based on the biased NMOS degeneration and the biased PMOS degeneration.

21. The apparatus of claim 20, wherein the inverting means comprises:

a primary PMOS transistor; and

a primary NMOS transistor coupled to the primary PMOS transistor,

wherein a gate of the primary PMOS transistor and a gate of the primary NMOS transistor is coupled to an input of the ring oscillator stage, and

wherein a drain of the primary PMOS transistor and a drain of the primary NMOS transistor are coupled to an output of the ring oscillator stage.

22. The apparatus of claim 21, wherein the PMOS biasing means comprises a first secondary PMOS transistor, a second secondary PMOS transistor, a third secondary PMOS transistor, and a fourth secondary PMOS transistor,

wherein a source of the primary PMOS transistor is coupled to a drain of the first secondary PMOS transistor, a drain of the second secondary PMOS transistor, a drain of the third secondary PMOS transistor, and a drain of the fourth secondary PMOS transistor,

wherein a source of the first secondary PMOS transistor, a source of the second secondary PMOS transistor, a source of the third secondary PMOS transistor, and a source of the fourth secondary PMOS transistor is coupled to the supply voltage,

wherein a resistance of each of the first secondary PMOS transistor, the second secondary PMOS transistor, the third secondary PMOS transistor, and the fourth secondary PMOS transistor is controlled based on the supply voltage by respectively receiving the first bias signal from the voltage biasing module, and

wherein each of the first secondary PMOS transistor, the second secondary PMOS transistor, the third secondary PMOS transistor, and the fourth secondary PMOS transistor receives the first bias signal via a respective gate node.

23. The apparatus of claim 22, wherein the NMOS biasing means comprises a first secondary NMOS transistor, a second secondary NMOS transistor, a third secondary NMOS transistor, and a fourth secondary NMOS transistor,

wherein a source of the primary NMOS transistor is coupled to a drain of the first secondary NMOS transistor, a drain of the second secondary NMOS transistor, a drain of the third secondary NMOS transistor, and a drain of the fourth secondary NMOS transistor,

wherein a source of the first secondary NMOS transistor, a source of the second secondary NMOS transistor, a source of the third secondary NMOS transistor, and a source of the fourth secondary NMOS transistor is coupled to a ground node,

wherein a resistance of each of the first secondary NMOS transistor, the second secondary NMOS transistor, the third secondary NMOS transistor, and the fourth secondary NMOS transistor is controlled based on the supply voltage by respectively receiving the second bias signal from voltage biasing module, and

wherein each of the first secondary NMOS transistor, the second secondary NMOS transistor, the third secondary NMOS transistor, and the fourth secondary NMOS transistor receives the second bias signal via a respective gate node.

24. The apparatus of claim 23,

wherein the drain of the first PMOS transistor is coupled to the gate of the first secondary PMOS transistor, the gate of the second secondary PMOS transistor, the gate of the third secondary PMOS transistor, and the gate of the fourth secondary PMOS transistor.

25. The apparatus of claim 24,

wherein the drain of the NMOS transistor is coupled to the gate of the first secondary PMOS transistor, the gate of the second secondary PMOS transistor, the gate of the third secondary PMOS transistor, and the gate of the fourth secondary PMOS transistor,

wherein a source of the NMOS transistor is coupled to the ground node, and wherein the gate of the NMOS transistor is coupled to the gate of the first secondary NMOS transistor, the gate of the second secondary NMOS transistor, the gate of the third secondary NMOS transistor, and the gate of the fourth secondary NMOS transistor.

26. The apparatus of claim 23,

wherein a second node of the current source is coupled to the ground node.