Vector signaling with reduced receiver complexity

• US 9,692,555 B2
• Filed: 11/01/2016
• Issued: 06/27/2017
• Est. Priority Date: 05/20/2010
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Shokrollahi, Amin
• Primary Examiner(s): Flores, Leon
• Application Number:
  US15/340,415
• Publication Number:
  US 20170048024A1
• Time in Patent Office: 238 Days
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0052 Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 17/18 Code selection mechanisms

Abstract

Methods and apparatuses are described to determine subsets of vector signaling codes capable of detection by smaller sets of comparators than required to detect the full code. The resulting lower receiver complexity allows systems utilizing such subset codes to be less complex and require less power.

Claims

1. An apparatus comprising:

a multi-wire bus configured to receive a set of symbols;

a first two-input comparator connected to the multi-wire bus configured to receive a pair of symbols of the set of symbols and to responsively generate a first output of a set of outputs, the symbols in the pair of symbols having different values;

an arithmetic circuit configured to receive the pair of symbols and to responsively generate an arithmetic result; and

a second two-input comparator configured to receive (i) the arithmetic result and (ii) a third symbol from the set of symbols, the third symbol not in the pair of symbols, and to responsively generate a second output of the set of outputs, the second output representing a comparison of the arithmetic result to the third symbol.

2. The apparatus of claim 1, wherein at least one of the pair of symbols has a symbol value of ‘

0’

.

3. The apparatus of claim 2, wherein the pair of symbols are selected from a set of permutations of [−

1,0] and [1,0].

4. The apparatus of claim 1, wherein the arithmetic result represents a sum of the pair of symbols.

5. The apparatus of claim 1, wherein the arithmetic result represents an average of the pair of symbols.

6. The apparatus of claim 1, wherein the first and second outputs are binary output bits.

7. The apparatus of claim 1, further comprising:

a plurality of arithmetic circuits configured to generate the set of symbols, each arithmetic circuit configured to operate on a corresponding pair of symbols of a second set of symbols received on a second multi-wire bus; and

a plurality of local sparse comparator units configured to generate at least two outputs of the set of outputs, each local SCU configured to compare a corresponding pair of symbols of the second set of symbols received on adjacent wires of the second multi-wire bus.

8. The apparatus of claim 7, wherein each pair of symbols of the second set of symbols received on adjacent wires have different values.

9. The apparatus of claim 8, wherein one symbol in each pair of symbols of the second set of symbols received on adjacent wires has a ‘

0’

value.

10. The apparatus of claim 9, wherein the plurality of local sparse comparator units comprises three two-input comparators configured to provide a third, a fourth, and a fifth output.

11. A method comprising:

receiving a set of symbols via a multi-wire bus;

generating a first output of a set of outputs using a first two-input comparator connected to the multi-wire bus, the first output based on a comparison of a pair of symbols of the set of symbols, the symbols in the pair of symbols having different values;

generating, using an arithmetic circuit receiving the pair of symbols, an arithmetic result; and

generating a second output of the set of outputs using a second two-input comparator receiving (i) the arithmetic result and (ii) a third symbol from the set of symbols, the third symbol not in the pair of symbols, the second output representing a comparison of the arithmetic result to the third symbol.

12. The method of claim 11, wherein at least one of the pair of symbols has a symbol value of ‘

0’

.

13. The method of claim 12, wherein the pair of symbols are selected from a set of permutations of [−

1,0] and [1,0].

14. The method of claim 11, wherein the arithmetic result represents a sum of the pair of symbols.

15. The method of claim 11, wherein the arithmetic result represents an average of the pair of symbols.

16. The method of claim 11, wherein the first and second outputs are binary output bits.

17. The method of claim 11, further comprising:

generating the set of symbols using a plurality of arithmetic circuits, each arithmetic circuit operating on a corresponding pair of symbols of a second set of symbols received on a second multi-wire bus; and

and generating a plurality of outputs of the set of outputs using a plurality of local sparse comparator units, each output of the plurality of outputs generated by comparing a corresponding pair of symbols of the second set of symbols received on adjacent wires of the second multi-wire bus.

18. The method of claim 17, wherein each pair of symbols of the second set of symbols received on adjacent wires have different values.

19. The method of claim 18, wherein one symbol in each pair of symbols of the second set of symbols received on adjacent wires has a ‘

0’

value.

20. The method of claim 19, wherein the plurality of outputs comprises a third, a fourth, and a fifth output generated by three local sparse comparator units.