Measuring power consumption of circuit component operating in run mode
First Claim
1. A method of measuring power consumption of an integrated circuit (IC) chip, the method comprising:
- measuring a voltage drop across a resistor coupled to a power terminal of the IC chip located outside the IC chip and a system power source terminal located outside the IC chip, the power terminal for providing power from the system power source to components in the IC chip;
amplifying the voltage drop using an on-chip amplifier, the on-chip amplifier including a first input coupled to the power terminal and a second input coupled to the system power source terminal;
converting the amplified voltage drop to digital data using an on-chip analog-to -digital converter (ADC);
determining a time of measurement; and
storing the time of measurement and digital data.
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Accused Products
Abstract
A sense resistor is coupled between a power source and one or more power pins of an integrated circuit (IC) chip including a circuit component (e.g., a microcontroller unit (MCU)). An on-chip amplifier (e.g., a programmable gain amplifier or op-amp) amplifies the voltage drop over the sense resistor to a level that is within the dynamic range of an on-chip analog-to-digital converter (ADC). In some implementations, the measured signals can be time-stamped and stored in a trace buffer and aligned with other trace data using a front-end tool (e.g., a personal computer). In some implementations, circuitry is included for detecting and handling power consumption events associated with the circuit component. In some implementations, a program counter associated with the circuit component is synchronously sampled with the power consumption measurements and/or other data sources.
20 Citations
20 Claims
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1. A method of measuring power consumption of an integrated circuit (IC) chip, the method comprising:
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measuring a voltage drop across a resistor coupled to a power terminal of the IC chip located outside the IC chip and a system power source terminal located outside the IC chip, the power terminal for providing power from the system power source to components in the IC chip; amplifying the voltage drop using an on-chip amplifier, the on-chip amplifier including a first input coupled to the power terminal and a second input coupled to the system power source terminal; converting the amplified voltage drop to digital data using an on-chip analog-to -digital converter (ADC); determining a time of measurement; and storing the time of measurement and digital data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An integrated circuit (IC) chip comprising:
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an amplifier, included in the IC chip, and configured for amplifying a voltage drop across a sense resistor coupled to a power terminal of the IC chip located outside the IC chip and a system power source terminal located outside the IC chip, the on-chip amplifier including a first input coupled to the power terminal and a second input coupled to the system power source terminal, the power terminal for providing power from the system power source to one or more components in the IC chip; an analog-to-digital converter (ADC), in the IC chip, and configured for converting the amplified voltage drop to digital data; and a trace buffer coupled to the ADC and configured for storing the digital data. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. An integrated circuit (IC) chip comprising:
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an amplifier having a first input coupled to a power terminal of the IC chip for powering components of the IC chip, and a second input coupled a system power source terminal, the amplifier configured for amplifying a voltage drop across the power terminal and the system power source terminal; an analog-to-digital converter (ADC), in the IC chip, and configured for converting the amplified voltage drop to digital data in response to a trigger signal; a program counter (PC) operable to indicate a current location in a software program; a delay circuit responsive to the trigger signal, the delay circuit configured to generate a latch signal by adjusting the trigger signal according to an ADC conversion time; and a PC latch circuit coupled to the delay circuit, the PC latch circuit configured to sample the PC counter in response to the latch signal. - View Dependent Claims (19, 20)
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Specification