Energy-focused compiler-assisted branch prediction
First Claim
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1. A memory device having instructions stored thereon that, in response to execution by a processor, cause the processor to perform operations to:
- access control information of an instruction sequence at runtime, the control information added in the instruction sequence prior to runtime to prevent coded information corresponding to a control-flow changing instruction from being decoded in a pipeline of the processor at runtime; and
use the control information to predict an outcome of the control-flow changing instruction, the outcome comprising a target of the control-flow changing instruction that includes a path following the control-flow changing instruction, and to fetch an instruction corresponding to the path.
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Abstract
A processing system to reduce energy consumption and improve performance in a processor, controlled by compiler inserted information ahead of a selected branch instruction, to statically expose and control how the prediction should be completed and which mechanism should be used to achieve energy and performance efficiency.
279 Citations
20 Claims
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1. A memory device having instructions stored thereon that, in response to execution by a processor, cause the processor to perform operations to:
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access control information of an instruction sequence at runtime, the control information added in the instruction sequence prior to runtime to prevent coded information corresponding to a control-flow changing instruction from being decoded in a pipeline of the processor at runtime; and use the control information to predict an outcome of the control-flow changing instruction, the outcome comprising a target of the control-flow changing instruction that includes a path following the control-flow changing instruction, and to fetch an instruction corresponding to the path. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A system for use with a processor, the system comprising:
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microarchitecture capable of accessing control information of an instruction sequence at runtime, the control information added in the instruction sequence prior to runtime to prevent coded information corresponding to a control-flow changing instruction from being decoded in a pipeline of the processor at runtime; and the microarchitecture capable of using the control information to predict an outcome of the control-flow changing instruction, the outcome comprising a target of the control-flow changing instruction that includes a path following the control-flow changing instruction, and to fetch an instruction corresponding to the path. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method for use with a processor, the method comprising:
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with respect to an instruction sequence including a control-flow changing instruction to affect a control-flow of the instruction sequence to which control information has been added, removing the control-flow changing instruction from the instruction sequence; wherein the control information is to be utilized at runtime to predict an outcome of the control-flow changing instruction, the outcome comprising a target of the control-flow changing instruction that includes a path following the control-flow changing instruction, and to fetch an instruction corresponding to the path. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification