Encryption integrity check with CRC encryption in memory using a word count- and address-derived nonce
First Claim
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1. A memory, comprising:
- a non-volatile memory device; and
a controller coupled to the memory device and comprising logic to;
receive a write request from a host device to write a line of data having a logical block address to the memory device at a physical memory address, where the physical memory address includes a write count that is incremented for each write operation;
generate a first plaintext cyclic redundancy check (CRC) from a concatenation of the line of data and the logical block address;
encrypt, by a first encoder, the line of data to generate an encrypted line of data;
encrypt, by a second encoder, a nonce formed from a concatenation of the write count and the physical memory address to generate an encrypted value that is unique to the write request;
perform an XOR operation with the first plaintext CRC and the encrypted value to generate a first encrypted CRC; and
store the encrypted line of data and the first encrypted CRC in the memory device to complete the write request.
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Abstract
Apparatus, systems, and methods for AES integrity check in memory are described. In one embodiment, a controller comprises logic to receive a write request from a host device to write a line of data to the memory device, determine a first plaintext cyclic redundancy check from the line of data, encrypt the line of data, encrypt the first plaintext CRC with a unique value to generate a first encrypted CRC, and store the encrypted line of data and the first encrypted CRC in memory. Other embodiments are also disclosed and claimed.
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Citations
24 Claims
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1. A memory, comprising:
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a non-volatile memory device; and a controller coupled to the memory device and comprising logic to; receive a write request from a host device to write a line of data having a logical block address to the memory device at a physical memory address, where the physical memory address includes a write count that is incremented for each write operation; generate a first plaintext cyclic redundancy check (CRC) from a concatenation of the line of data and the logical block address; encrypt, by a first encoder, the line of data to generate an encrypted line of data; encrypt, by a second encoder, a nonce formed from a concatenation of the write count and the physical memory address to generate an encrypted value that is unique to the write request; perform an XOR operation with the first plaintext CRC and the encrypted value to generate a first encrypted CRC; and store the encrypted line of data and the first encrypted CRC in the memory device to complete the write request. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An electronic device, comprising:
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a processor; and a memory device, comprising; a non-volatile memory device; and a controller coupled to the memory device and comprising logic to; receive a write request from a host device to write a line of data having a logical block address to the memory device at a physical memory address, where the physical memory address includes a write count that is incremented for each write operation; generate a first plaintext cyclic redundancy check (CRC) from a concatenation of the line of data and the logical block address; encrypt, by a first encoder, the line of data to generate an encrypted line of data; encrypt, by a second encoder, a nonce formed from a concatenation of the write count and the physical memory address to generate an encrypted value that is unique to the write request; perform an XOR operation with the first plaintext CRC and the encrypted value to generate a first encrypted CRC; and store the encrypted line of data and the first encrypted CRC in the memory device to complete the write request. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A computer program product comprising logic instructions stored on a nontransitory computer readable medium which, when executed by a controller coupled to a memory device, configure the controller to:
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receive a write request from a host device to write a line of data having a logical block address to a memory device at a physical memory address, where the physical memory address includes a write count that is incremented for each write operation; generate a first plaintext cyclic redundancy check (CRC) from a concatenation of the line of data and the logical block address; encrypt, by a first encoder, the line of data to generate an encrypted line of data; encrypt, by a second encoder, a nonce formed from a concatenation of the write count and the physical memory address to generate an encrypted value that is unique to the write request; perform an XOR operation with the first plaintext CRC and the encrypted value to generate a first encrypted CRC; and store the encrypted line of data and the first encrypted CRC in the memory device to complete the write request. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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Specification