Integrated circuits having in-situ constraints

• US 9,697,317 B1
• Filed: 05/03/2013
• Issued: 07/04/2017
• Est. Priority Date: 04/21/2004
• Status: Active Grant

• Current Assignee: IYM Technologies LLC (General Patent Corporation)
• Original Assignee: IYM Technologies LLC (General Patent Corporation)
• Inventors: Qian, Qi-De
• Primary Examiner(s): Sayadian, Hrayr A
• Application Number:
  US13/886,577
• Time in Patent Office: 1,523 Days
• Field of Search: 716122, 716 11, 716 8, 716 9, 716 10, 716 19, 716 20, 716 21
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G06F 30/323 Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

An integrated device product having objects positioned in accordance with in-situ constraints. Said in-situ constraints comprise predetermined constraints and their local modifications. These local modifications, individually formulated for a specific pair of objects, account for on-the-spot conditions that influence the optimal positioning of the objects. The present invention improves the yield of integrated devices by adding local process modification distances to the predetermined constraints around processing hotspots thus adding extra safety margin to the device yield.

Claims

1. An integrated circuit product prepared by a process comprising the steps of:

receiving a design layout comprising a plurality of layout objects residing on a plurality of layers;

receiving descriptions of a manufacturing process;

constructing a system of initial constraints among said layout objects;

computing one or more local process modifications to change said initial constraints using said descriptions of manufacturing process;

constructing new local constraint distances by combining said local process modifications with constraint distances in said system of initial constraints;

enforcing said new local constraint distances;

updating the coordinate variables of said layout objects according to the solutions obtained from enforcing said new local constraint distances, thereby obtaining updated coordinate variables of said layout objects; and

fabricating the integrated circuit product in accordance with the updated coordinate variables, wherein the integrated circuit product comprises a first plurality of routing wires running in a first direction, and a second plurality of routing wires running in a second direction, the second direction being orthogonal to the first direction, the routing wires of the first plurality of routing wires having first width values, the routing wires of the second plurality of routing wires having second width values, the first width values being substantially different from the second width values.

2. The integrated circuit product of claim 1, wherein the process further checking said design layout against design rules.

3. The integrated circuit product of claim 1, wherein the step of computing one or more local process modifications comprises simulating the fabrication process selected from the group consisting of:

lithography and etching.

4. The integrated circuit product of claim 1, wherein the step of computing one or more local process modifications comprises computing a distance of a modification from simulated contours.

5. The integrated circuit product of claim 1, wherein the step of enforcing said new local constraint distances comprises modifying one or more distances between layout objects of the plurality of layout objects.

6. The integrated circuit product of claim 1, wherein the step of receiving initial a design layout comprises receiving one or more layouts selected from the group consisting of:

layouts of standard cells, layouts of memories, layouts of metal routing layers, layouts of input circuits, and layouts of output circuits.

7. The integrated circuit product of claim 1, wherein the step descriptions of the manufacturing process are selected from the group consisting of:

design rules, simulation models, equipment settings, material selections, and look up data tables.

8. The integrated circuit product of claim 1, wherein the step of constructing comprises constructing constraints from design rules.

9. The integrated circuit product of claim 1, wherein said step of computing one or more local process modifications comprises detecting processing hotspots.