Vertical bit vector shift in memory
First Claim
Patent Images
1. A method for shifting data, comprising:
- storing a vertical bit vector of data in a memory array, wherein;
the vertical bit vector is stored in memory cells coupled to a sense line and a plurality of access lines; and
the vertical bit vector is separated by at least one sense line from a neighboring vertical bit vector; and
performing, using sensing circuitry, a vertical bit vector shift of elements of the vertical bit vector by performing a first AND operation with an element of a vertical shift bit vector and an element of the vertical bit vector that is being shifted.
8 Assignments
0 Petitions
Accused Products
Abstract
Examples of the present disclosure provide apparatuses and methods for vertical bit vector shift in a memory. An example method comprises storing a vertical bit vector of data in a memory array, wherein the vertical bit vector is stored in memory cells coupled to a sense line and a plurality of access lines and the vertical bit vector is separated by at least one sense line from a neighboring vertical bit vector; and performing, using sensing circuitry, a vertical bit vector shift of a number of elements of the vertical bit vector.
339 Citations
30 Claims
-
1. A method for shifting data, comprising:
-
storing a vertical bit vector of data in a memory array, wherein; the vertical bit vector is stored in memory cells coupled to a sense line and a plurality of access lines; and the vertical bit vector is separated by at least one sense line from a neighboring vertical bit vector; and performing, using sensing circuitry, a vertical bit vector shift of elements of the vertical bit vector by performing a first AND operation with an element of a vertical shift bit vector and an element of the vertical bit vector that is being shifted. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
-
-
13. A method for shifting data, comprising:
-
storing bit vectors of data in a memory array, wherein; each bit vector is stored in memory cells coupled to a sense line and a plurality of access lines; and each bit vector is separated by at least one sense line from a neighboring bit vector; and shifting elements of the bit vectors by; performing shift operations, wherein each of the shift operations shift elements of the bit vectors of data by a number of positions indicated by a vertical shift bit vector and wherein elements of each of the vertical shift bit vectors coupled to common access lines include at least one of values 1 and 0 and wherein a value of 1 indicates that corresponding bit vectors are shifted and a value of 0 indicates that corresponding bit vectors are not shifted or a value of 0 indicates that corresponding bit vectors are shifted and a value of 1 indicates that corresponding bit vectors are not shifted. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
-
-
21. An apparatus comprising:
-
a first group of memory cells coupled to a sense line and a first plurality of access lines and configured to store a number of elements of a vertical bit vector; and a controller configured to cause; shifting of the number of elements of the vertical bit vector by a number of positions indicated by a vertical shift bit vector, wherein elements of the vertical shift bit vector include at least one of values 1 and 0 and wherein a value of 1 indicates that corresponding bit vectors are shifted and a value of 0 indicates that corresponding bit vectors are not shifted or a value of 0 indicates that corresponding bit vectors are shifted and a value of 1 indicates that corresponding bit vectors are not shifted. - View Dependent Claims (22, 23, 24, 25)
-
-
26. An apparatus comprising:
-
a first group of memory cells coupled to a sense line and a first plurality of access lines and configured to store a number of elements of a vertical bit vector; and a controller configured to cause; performance of a number of shift operations on the number of elements of the vertical bit vector, wherein each of the number of shift operations shifts the elements of the vertical bit vector according to a number of elements of a vertical shift bit vector and wherein each of the number of shift operations includes performing a shift iteration on each of the number of elements of the vertical bit vector, wherein the shift iteration includes performing a first AND operation with an element of the number of vertical shift bit vectors and an element of the number of bit vectors that is being shifted. - View Dependent Claims (27, 28, 29)
-
-
30. A method for shifting data, comprising:
-
storing bit vectors of data in a memory array, wherein; each bit vector is stored in memory cells coupled to a sense line and a plurality of access lines; and each bit vector is separated by at least one sense line from a neighboring bit vector; and shifting elements of the bit vectors by; performing shift operations, wherein each of the shift operations shift elements of the bit vectors of data by a number of positions indicated by a vertical shift bit vector, wherein performing the shift operations includes performing a shift iteration on each element of each of the bit vectors that are coupled to a common access line by an amount indicated by elements of the vertical shift bit vector, and wherein performing the shift iteration includes inverting an element of the vertical shift bit vector, performing an AND operation with the inverted element of the vertical shift bit vector and an element of the bit vectors, and storing the result of the AND operation in destination memory cells corresponding to the element of the bit vectors.
-
Specification