Variable width memory module supporting enhanced error detection and correction

• US 9,697,884 B2
• Filed: 09/12/2016
• Issued: 07/04/2017
• Est. Priority Date: 10/08/2015
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Linstadt, John Eric, Wright, Kenneth L., Ware, Frederick A.
• Primary Examiner(s): Le, Vu
• Application Number:
  US15/262,741
• Publication Number:
  US 20170103800A1
• Time in Patent Office: 295 Days
• Field of Search: 36518902, 36518917, 36518905
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals

Abstract

Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable, and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

Claims

1. A memory module comprising:

a primary data interface to communicate data responsive to module commands;

memory components, including a first memory component and a second memory component; and

a buffer component connected between the primary data interface and each of the first memory component and the second memory component, the buffer component supporting a first access mode and a time-division-multiplexing mode;

wherein the buffer component;

in the first access mode, transports first data between the primary data interface and one of the first memory component and the second memory component responsive to a first module command; and

in the time-division-multiplexing mode, transports second data between the primary data interface and each of the first memory component and the second memory component responsive to a second module command.

2. The memory module of claim 1, wherein the first data is of a first data width of a first number of data bits, the second data is of a second data width of a second number, greater than the first number, of data bits.

3. The memory module of claim 2, wherein the first number of data bits is half the second number of data bits.

4. The memory module of claim 1, wherein the buffer component interleaves first read data from the first memory component with second read data from the second memory component in the time-division-multiplexing mode.

5. The module of claim 1, wherein the buffer component conveys the first data to the primary data interface at a first bit rate in the first access mode, and conveys the second data to the primary data interface at a second bit rate, wherein the second bit rate is twice the first bit rate in the time-division-multiplexing mode.

6. The memory module of claim 1, further comprising a mode register to store a value indicative of one of the first access mode and the time-division-multiplexing mode.

7. The memory module of claim 1, further comprising a third memory component and a fourth memory component, the buffer component connected between the primary data interface and each of the third memory component and the fourth memory component.

8. The memory module of claim 7, wherein the buffer component:

in the first access mode, transports third data in parallel with the first data between the primary data interface and one of the third memory component and the fourth memory component responsive to the first module command; and

in the time-division-multiplexing mode, transports fourth data in parallel with the second data between the primary data interface and each of the third memory component and the fourth memory component responsive to the second module command.

9. The memory module of claim 8, the buffer component supporting a narrow time-division-multiplexing mode, wherein the buffer component interleaves the first data with the third data.

10. A memory module comprising:

a module command interface to receive module commands;

an address buffer component coupled to the module command interface to receive the module commands, the address buffer component including a secondary command interface;

memory slices coupled to the primary data interface and the secondary command interface, each memory slice including;

first, second, third, and fourth memory components each coupled to the secondary command interface;

a data-buffer component including;

first, second, third, and fourth memory-component interfaces of a memory-component width and respectively coupled to the first, second, third, and fourth memory components;

first and second primary data interfaces, each of the memory-component width, to communicate module data responsive to the module commands; and

multiplexing logic to convey;

in a first access mode, first data from only two of the first, second, third, and fourth memory components responsive to a first module command; and

in a time-division-multiplexing mode, second data from successive pairs of the first, second, third, and fourth memory components responsive to a second module command.

11. The memory module of claim 10, wherein the address buffer component is coupled to the data-buffer components to control the multiplexing logic.

12. The memory module of claim 11, wherein the address buffer component further comprises a mode register to store a value indicative of one of the first access mode and the time-division-multiplexing mode.

13. The memory module of claim 10, wherein the first data is of a first data width of a first number of data bits, and the second data is of the first data width.

14. The memory module of claim 13, wherein the data-buffer component of each of the memory slices supports a second time-division-multiplexing mode, wherein the multiplexing logic interleaves third data of a second data width half the first data width from only two of the first, second, third, and fourth memory components.

15. A memory module comprising:

a primary data interface having primary data links;

memory components; and

at least one data buffer component connected between the primary data interface and the memory components, the at least one data buffer component supporting a full-width mode, a half-width first access mode, and a half-width time-division-multiplexing mode;

wherein the at least one data buffer component;

in the full-width mode, communicates first data between the memory components and all the primary data links responsive to a first module command;

in the half-width first access mode, communicates second data between a number of the memory components and half of the primary data links responsive to a second module command; and

in the half-width time-division-multiplexing mode, communicates third data between twice the number of the memory components and half of the primary data links responsive to a third module command.

16. The memory module of claim 15, wherein the third module command comprises a read command, and wherein the at least one data buffer component interleaves the third data from the number of memory components responsive to the read command.

17. The memory module of claim 15, wherein the at least one data buffer component communicates the third data with the twice the number of the memory components at a first bit rate, and communicates the third data with the primary data interface at a second bit rate twice the first bit rate.

18. The memory module of claim 15, wherein the primary data links consist of eighteen groups of nibble-wide data link groups, and wherein the at least one data buffer component communicates four sets of nine data nibbles responsive to the second module command and eight sets of nine data nibbles responsive to the third module command.

19. The memory module of claim 18, wherein the at least one data buffer component communicates four sets of eighteen data nibbles responsive to the first module command.

20. The memory module of claim 19, the at least one data buffer component supporting a second full width mode in which that at least one data buffer component communicates eight sets of eighteen data nibbles responsive to a fourth module command.

21. A data buffer component comprising:

an interface to couple to memory components;

a primary data interface to receive module commands; and

circuitry to support a full-width mode, a half-width first access mode, and a half-width time-division-multiplexing mode, wherein;

in the full-width mode, the data buffer component communicates first data between the memory components and all the primary data links responsive to a first module command;

in the half-width first access mode, the data buffer component communicates second data between a number of the memory components and half of the primary data links responsive to a second module command; and

in the half-width time-division-multiplexing mode, the data buffer component communicates third data between twice the number of the memory components and half of the primary data links responsive to a third module command.