Semiconductor device and semiconductor module

• US 9,697,948 B2
• Filed: 11/10/2014
• Issued: 07/04/2017
• Est. Priority Date: 11/13/2013
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Osada, Kosei, Kagawa, Tetsuya, Mifuji, Michihiko, Kasahara, Nobuyuki, Kageyama, Satoshi, Nishimura, Isamu, Yanagishima, Daiki, Ishikawa, Toshiyuki
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): DINKE, BITEW A
• Application Number:
  US14/537,234
• Publication Number:
  US 20150137314A1
• Time in Patent Office: 967 Days
• CPC Class Codes: H01F 2027/2819 Planar transformers with printed windings, e.g. surrounded by two cores and to be mounted on printed circuit
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01F 27/288 Shielding
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/10272 Silicon Carbide [SiC]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip

Abstract

The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.

Claims

1. A semiconductor device comprising:

an insulating layer;

a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in a vertical direction;

a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in plan view and is connected with potential lower than the high voltage coil, the low potential portion including

a low voltage pad which is exposed to a surface of the insulating layer, and

low voltage wiring which is connected between the low voltage coil and the low voltage pad, the low voltage wiring including a lead-out wiring formed in a linear shape, the lead-out wiring being led out from the low voltage coil at a position lower than a position of the low voltage coil in the vertical direction to a region under the low voltage pad; and

an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member, the electrically floated metal member being arranged away from the high voltage region in a horizontal direction and between the high voltage coil and the low voltage pad, and crossing the lead-out wiring in plan view.

2. The semiconductor device according to claim 1, wherein the electric field shield portion includes a capacitor composed of a plurality of electrode plates which face each other at intervals in a horizontal direction.

3. The semiconductor device according to claim 2, wherein three or more electrode plates are provided at equal intervals.

4. The semiconductor device according to claim 2, wherein three or more electrode plates are provided at unequal intervals.

5. The semiconductor device according to claim 1, wherein

the insulating layer includes an insulating film laminated structure including a plurality of insulating films which are laminated successively,

the high voltage coil and the low voltage coil are respectively embedded in separate insulating films,

one or more insulating films are interposed between the high voltage coil and the low voltage coil, and

the electric field shield portion includes electrode plates which are embedded in at least one insulating film.

6. The semiconductor device according to claim 5, wherein a plurality of electrode plates face the same insulating layer at intervals and constitute a capacitor.

7. The semiconductor device according to claim 6, wherein three or more electrode plates are provided at equal intervals.

8. The semiconductor device according to claim 6, wherein three or more electrode plates are provided at unequal intervals.

9. The semiconductor device according to claim 5, wherein the electrode plates are provided in the same insulating layer independently so as not to overlap each other in a horizontal direction.

10. The semiconductor device according to claim 5, wherein the electrode plates are embedded in an insulating film for the high voltage coil, an insulating film for the low voltage coil, and an insulating film disposed therebetween.

11. The semiconductor device according to claim 10, wherein the electrode plates embedded in the respective insulating films are arranged continuously in a vertical direction.

12. The semiconductor device according to claim 5, wherein the electrode plates are embedded selectively in an insulating film for the high voltage coil and an insulating film for the low voltage coil.

13. The semiconductor device according to claim 5, wherein

the low potential portion includes a shield field layer which is embedded in a plurality of insulating films so as to surround the high voltage region, and

the electrode plates are embedded in the same insulating film as the shield layer.

14. The semiconductor device according to claim 5, wherein

the high voltage coil is an upper coil which is disposed at a side relatively near to a surface of the insulating film laminated structure and the low voltage coil is a lower coil which is disposed below the upper coil, and

the low potential portion includes low voltage wiring which is connected with the lower coil and penetrates the insulating film laminated structure in a lamination direction.

15. The semiconductor device according to claim 14, wherein the low potential portion includes a low voltage pad which is exposed to a surface of the insulating layer laminated structure and is connected with the low voltage wiring.

16. The semiconductor device according to claim 1, wherein a distance L1 between the high voltage coil and the electric field shield portion in a horizontal direction is larger than a distance L2 between the high voltage coil and the low voltage coil in a vertical direction.

17. The semiconductor device according to claim 1, wherein the electric field shield portion surrounds the high voltage coil.

18. The semiconductor device according to claim 1, further comprising a substrate arranged to support the insulating layers,

wherein the low voltage coil is connected with the substrate.

19. A semiconductor module comprising:

a semiconductor device including;

an insulating layer;

a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in a vertical direction;

a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in plan view and is connected with potential lower than the high voltage coil, the low potential portion including

a low voltage pad which is exposed to a surface of the insulating layer, and

low voltage wiring which is connected between the low voltage coil and the low voltage pad, the low voltage wiring including a lead-out wiring formed in a linear shape, the lead-out wiring being led out from the low voltage coil at a position lower than a position of the low voltage coil in the vertical direction to a region under the low voltage pad; and

an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member, the electrically floated metal member being arranged away from the high voltage region in a horizontal direction and between the high voltage coil and the low voltage pad, and crossing the lead-out wiring in plan view;

a low voltage element which is electrically connected with the low voltage coil of the semiconductor device;

a high voltage element which is electrically connected with the high voltage coil of the semiconductor device; and

a resin package arranged to collectively seal the semiconductor device, the low voltage element and the high voltage element.

20. A semiconductor device, comprising:

an insulating layer including a first portion and a second portion that are disposed at an interval in a vertical direction, the insulating layer including first and second regions in a horizontal direction, the second region including a portion surrounding the first region in plan view, the second region including a low potential area, the low potential area including

a low voltage pad which is exposed to a surface of the insulating layer, and

low voltage wiring which is connected between the low voltage coil and the low voltage pad, the low voltage wiring including a lead-out wiring formed in a linear shape, the lead-out wiring being led out from the low voltage coil at a position lower than a position of the low voltage coil in the vertical direction to a region under the low voltage pad;

a high voltage coil disposed in the first region and in the first portion of the insulating layer;

a low voltage coil disposed in the first region and in the second portion of the insulating layer;

an element provided in the low potential area and being connected to a potential lower than a potential supplied to the high voltage coil; and

an electric field shield disposed in the second region of the insulating layer and including an electrically floating metal member, the electrically floated metal member being arranged away from the high voltage region in a horizontal direction and between the high voltage coil and the low voltage pad, and crossing the lead-out wiring in plain view.