Deposition method and method for manufacturing semiconductor device

• US 9,698,008 B2
• Filed: 04/07/2015
• Issued: 07/04/2017
• Est. Priority Date: 04/16/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Furuno, Makoto, Yamazaki, Shunpei, Sakata, Junichiro
• Primary Examiner(s): Lee, Cheung
• Application Number:
  US14/680,159
• Publication Number:
  US 20150214043A1
• Time in Patent Office: 819 Days
• CPC Class Codes: C23C 14/0036 Reactive sputtering
• CPC Class Codes: C23C 14/08 Oxides C23C14/10 takes precedence
• CPC Class Codes: C23C 14/3407 Cathode assembly for sputtering apparatus, e.g. Target
• CPC Class Codes: C23C 14/3414 Metallurgical or chemical aspects of target preparation, e.g. casting, powder metallurgy
• CPC Class Codes: H01L 21/02112 characterised by the material of the layer
• CPC Class Codes: H01L 21/02266 deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
• CPC Class Codes: H01L 21/8232 Field-effect technology
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/70 : the floating gate being an electrode shared by two or more components

Abstract

An object is to provide a deposition method in which a gallium oxide film is formed by a DC sputtering method. Another object is to provide a method for manufacturing a semiconductor device using a gallium oxide film as an insulating layer such as a gate insulating layer of a transistor. An insulating film is formed by a DC sputtering method or a pulsed DC sputtering method, using an oxide target including gallium oxide (also referred to as GaO_X). The oxide target includes GaO_X, and X is less than 1.5, preferably more than or equal to 0.01 and less than or equal to 0.5, further preferably more than or equal to 0.1 and less than or equal to 0.2. The oxide target has conductivity, and sputtering is performed in an oxygen gas atmosphere or a mixed atmosphere of an oxygen gas and a rare gas such as argon.

Claims

1. A semiconductor device comprising:

a first transistor comprising;

a channel formation region including a semiconductor material;

impurity regions with the channel formation region therebetween;

a first gate insulating layer over the channel formation region;

a first gate electrode overlapping with the channel formation region with the first gate insulating layer therebetween; and

a first source or drain electrode electrically connected to one of the impurity regions; and

a second transistor comprising;

a first insulating layer comprising gallium over the first transistor;

an oxide semiconductor layer over the first insulating layer;

a second source electrode or a second drain electrode electrically connected to the oxide semiconductor layer;

a second insulating layer comprising gallium over the oxide semiconductor layer and the second source electrode or the second drain electrode; and

a second gate electrode overlapping with the oxide semiconductor layer,

wherein the first insulating layer and the second insulating layer are in contact with the oxide semiconductor layer, and

wherein the second source electrode or the second drain electrode is electrically connected to the first gate electrode.

2. The semiconductor device according to claim 1, wherein the semiconductor material comprises any one of silicon, germanium, silicon germanium, silicon carbide and gallium arsenide.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises gallium.

4. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises indium, gallium and zinc.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor layer is an intrinsic oxide semiconductor layer or a substantially intrinsic oxide semiconductor layer.

6. The semiconductor device according to claim 1, wherein the second gate electrode is provided over the second insulating layer.

7. The semiconductor device according to claim 1, wherein the semiconductor device is incorporated into a memory element.

8. A semiconductor device comprising:

a first transistor comprising;

a channel formation region including a semiconductor material;

impurity regions with the channel formation region therebetween;

a first gate insulating layer over the channel formation region;

a first gate electrode overlapping with the channel formation region with the first gate insulating layer therebetween; and

a first source or drain electrode electrically connected to one of the impurity regions; and

a second transistor comprising;

a first insulating layer comprising gallium oxide over the first transistor;

an oxide semiconductor layer over the first insulating layer;

a second source electrode or a second drain electrode electrically connected to the oxide semiconductor layer;

a second insulating layer comprising gallium oxide over the oxide semiconductor layer and the second source electrode or the second drain electrode; and

a second gate electrode overlapping with the oxide semiconductor layer,

wherein the first insulating layer and the second insulating layer are in contact with the oxide semiconductor layer, and

wherein the second source electrode or the second drain electrode is electrically connected to the first gate electrode.

9. The semiconductor device according to claim 8, wherein the semiconductor material comprises any one of silicon, germanium, silicon germanium, silicon carbide and gallium arsenide.

10. The semiconductor device according to claim 8, wherein the oxide semiconductor layer comprises gallium.

11. The semiconductor device according to claim 8, wherein the oxide semiconductor layer comprises indium, gallium and zinc.

12. The semiconductor device according to claim 8, wherein the oxide semiconductor layer is an intrinsic oxide semiconductor layer or a substantially intrinsic oxide semiconductor layer.

13. The semiconductor device according to claim 8, wherein the second gate electrode is provided over the second insulating layer.

14. The semiconductor device according to claim 8, wherein the semiconductor device is incorporated into a memory element.