Structure and method for FinFET device

• US 9,698,058 B2
• Filed: 10/27/2015
• Issued: 07/04/2017
• Est. Priority Date: 04/25/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Fung, Ka-Hing, Ching, Kuo-Cheng, Chang, Chih-Sheng, Wu, Zhiqiang
• Primary Examiner(s): Landau, Matthew
• Assistant Examiner(s): WITHERS, GRANT S
• Application Number:
  US14/924,422
• Publication Number:
  US 20160049338A1
• Time in Patent Office: 616 Days
• Field of Search: None
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02233 of the semiconductor substrate or a semiconductor layer
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0603 characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions isolation regions between components H01L21/76; design considerations for integrated circuits H01L27/00; geometrical design considerations for devices H01L29/0657
• CPC Class Codes: H01L 29/0607 for preventing surface leakage or controlling electric field concentration
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66636 : with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/772 : Field effect transistors
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/7849 : the means being provided under the channel
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7855 : with at least two independent gates

Abstract

The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having a first gate region, a first fin structure over the substrate in the first gate region. The first fin structure includes an upper semiconductor material member, a lower semiconductor material member, surrounded by an oxide feature and a liner wrapping around the oxide feature of the lower semiconductor material member, and extending upwards to wrap around a lower portion of the upper semiconductor material member. The device also includes a dielectric layer laterally proximate to an upper portion of the upper semiconductor material member. Therefore the upper semiconductor material member includes a middle portion that is neither laterally proximate to the dielectric layer nor wrapped by the liner.

Claims

1. A method comprising:

forming a fin structure over a substrate;

after forming the fin structure over a substrate, forming an oxide feature around the fin structure such that a first portion of the fin structure is positioned above the oxide feature and a second portion of the fin structure is positioned below the oxide feature;

forming a liner layer directly on the second portion of the fin structure, the oxide feature and the first portion of the fin structure;

forming a dielectric layer on the liner layer;

removing a portion of the liner layer and a portion of the dielectric layer to expose the fin structure;

forming a gate dielectric layer on the fin structure, a remaining portion of the liner layer, and a remaining portion of the dielectric layer; and

forming a gate electrode on the gate dielectric layer.

2. The method of claim 1, wherein forming the fin structure over the substrate includes:

forming a first semiconductor material layer over the substrate;

forming a second semiconductor material layer over the first semiconductor material layer, the second semiconductor material layer being different that the first semiconductor material layer; and

patterning the first and second semiconductor material layers to form the fin structure.

3. The method of claim 2, wherein forming the oxide feature around the fin structure includes forming the oxide feature around the patterned first semiconductor material layer.

4. The method of claim 2, wherein forming the liner layer directly on the second portion of the fin structure, the oxide feature and the first portion of the fin structure includes forming the liner layer directly on a sidewall of the patterned second semiconductor material layer.

5. The method of claim 4, wherein after removing the portion of the liner layer and the portion of the dielectric layer to expose the fin structure, the sidewall of the patterned second semiconductor material layer is exposed.

6. The method of claim 5, wherein forming the gate dielectric layer on the fin structure, the remaining portion of the liner layer, and the remaining portion of the dielectric layer includes forming the gate dielectric layer directly on the exposed sidewall of the patterned second semiconductor material layer.

7. The method of claim 1, wherein after removing the portion the liner layer and the portion of the dielectric layer to expose the fin structure, the oxide feature remains covered by the remaining portion of the liner layer.

8. The method of claim 1, further comprising:

recessing a portion of the fin structure after removing the portion of the liner layer and the portion of the dielectric layer to expose the fin structure; and

forming a source/drain feature on the recessed portion of the fin structure.

9. The method of claim 1, wherein the liner layer includes a material selected from the group consisting of silicon nitride, silicon oxynitride and aluminum oxide.

10. The method of claim 1, wherein forming the fin structure over the substrate includes forming another fin structure over the substrate,

wherein forming the oxide feature around the fin structure includes performing an oxidation process, and

wherein the another fin structure is protected during the performing of the oxidation process thereby preventing an oxide feature from forming around the another fin structure.

11. A method comprising:

forming a first fin structure over a substrate, the first fin structure including;

a first semiconductor material layer; and

a second semiconductor material layer disposed over the first semiconductor material layer, the second semiconductor material layer being different than the first semiconductor material layer;

forming a liner layer extending along a sidewall of the first semiconductor material layer and along a sidewall of the second semiconductor material layer;

forming a dielectric isolation feature adjacent the first and second semiconductor material layers, wherein after forming the dielectric isolation feature, a first portion of the sidewall of the second semiconductor material layer is covered by the dielectric isolation feature and a second portion of the sidewall of the second semiconductor material layer is exposed;

forming a gate dielectric layer on the exposed second portion of the sidewall of the second semiconductor material layer;

forming a gate electrode layer over the gate dielectric;

forming a second fin structure over a substrate, the second fin structure including;

the first semiconductor material layer; and

the second semiconductor material layer disposed over the first semiconductor material layer; and

performing an oxidation process to form an oxide feature around the first semiconductor material layer of the second fin structure, wherein the first fin structure is protected during the performing of the oxidation process thereby preventing oxide from forming around the first semiconductor material layer of the first fin structure.

12. The method of claim 11, wherein the first fin structure further includes a third semiconductor material layer disposed over the second semiconductor material layer,

wherein after forming the dielectric isolation feature, a sidewall of the third semiconductor material layer is exposed, and

wherein forming the gate dielectric layer on the exposed second portion of the sidewall of the second semiconductor material layer includes forming the gate dielectric layer on the exposed sidewall of the third semiconductor material layer.

13. The method of claim 11, further comprising forming another liner layer on the liner layer extending along the sidewall of the first semiconductor material layer and along the sidewall of the second semiconductor material layer.

14. The method of claim 13, wherein forming the dielectric isolation feature adjacent the first and second semiconductor material layers includes forming the dielectric isolation feature directly on a portion of the liner layer and a portion of the another liner layer.

15. The method of claim 11, further comprising forming a hard mask layer extending along the sidewall of the first semiconductor material layer and along the sidewall of the second semiconductor material layer, and

removing the hard mask layer extending along the sidewall of the first semiconductor material layer and along the sidewall of the second semiconductor material layer prior to forming the liner layer extending along the sidewall of the first semiconductor material layer and along the sidewall of the second semiconductor material layer.

16. The method of claim 11, further comprising:

wherein forming the liner layer includes forming the liner layer extending along a sidewall of the first semiconductor material layer of the second fin structure and along a sidewall of the second semiconductor material layer of the second fin structure;

wherein forming the dielectric isolation feature includes forming another dielectric isolation feature adjacent the first and second semiconductor material layers of the second fin structure, wherein after forming the another dielectric isolation feature adjacent the first and second semiconductor material layers of the second fin structure, a first portion of the sidewall of the second semiconductor material layer of the second fin structure is covered by the another dielectric isolation feature and a second portion of the sidewall of the second semiconductor material layer of the second fin structure is exposed;

wherein forming the gate dielectric layer includes forming the gate dielectric on the exposed second portion of the sidewall of the second semiconductor material layer of the second fin structure; and

wherein forming the gate electrode over the gate dielectric includes forming the gate electrode over the gate dielectric on the second portion of the sidewall of the second semiconductor material layer of the second fin structure.

17. The method of claim 15, wherein the first semiconductor material layer includes silicon germanium,

wherein the second semiconductor material layer includes silicon, and

wherein the oxide feature includes silicon germanium oxide.

18. A method comprising:

providing a substrate having an n-type fin-like field-effect transistor (NFET) region and a p-type fin-like field-effect transistor (PFET) region;

forming first fin structures in the NFET region and the PFET region, the first fin structure includes;

a first epitaxial semiconductor material layer as its upper portion;

a second epitaxial semiconductor material layer, with a semiconductor oxide feature at its outer layer, as its middle portion; and

a third semiconductor material layer as its bottom portion;

forming a patterned oxidation-hard-mask (OHM) over the NFET region and PFET region to expose the first fin structure in a first gate region of the NFET region;

applying annealing to form a semiconductor oxide feature out of the second epitaxial semiconductor material layer in the first fin structure in the first gate region;

forming a liner wrapping over the first fin structures in both of the NFET region and the PFET region;

depositing a dielectric layer between the first fin structures;

recessing the liner in the PFET region after covering the NFET region with a hard mask layer;

forming a second fin structure in the PFET region while covering the NFET region with the hard mask layer;

recessing the liner in the NFET region after removing the hard mask layer; and

recessing the dielectric layer in both of the NFET region and the PFET region.

19. The method of claim 18, further comprising:

forming dummy gates in the first gate region and a second gate region in the second fin structure.

forming a first source/drain (S/D) features in a first S/D region in the first fin structure in the NFET;

forming a second S/D feature in a second S/D region in the second fin structure in the PFET;

replacing the dummy gates by a first high-k/metal gate (HK/MG) in the NFET region, including wrapping over an upper portion of the first fin structure in the first gate region; and

replacing the dummy gates by a second HK/MG in the PFET region, including wrapping over an upper portion of the second fin structure in a second gate region.

20. The method of claim 18, wherein further comprising:

controlling recessing the liner to have its top surface be above the second semiconductor material layer with a first distance; and

controlling recessing the dielectric layer to have its top surface be above the second semiconductor material layer with a second distance, which is larger than the first distance.