Semiconductor structure having a plurality of conductive paths

• US 9,698,099 B2
• Filed: 04/28/2015
• Issued: 07/04/2017
• Est. Priority Date: 10/12/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Cheng, Yi-Kan, Lee, Hui Yu, Kuan, Jui-Feng, Kuo, Feng Wei
• Primary Examiner(s): Tran, Long K
• Assistant Examiner(s): Vuong, Thai T
• Application Number:
  US14/698,168
• Publication Number:
  US 20150228576A1
• Time in Patent Office: 798 Days
• Field of Search: 257773
• CPC Class Codes: G03F 1/38 Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G03F 1/88 prepared by photographic processes for production of originals simulating relief
• CPC Class Codes: G06F 2119/10 Noise analysis or noise optimisation
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 2223/6638 Differential pair signal lines
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor structure includes a first conductive path and a second conductive path configured to carry a first pair of differential signals representative of an in-phase signal. The semiconductor device further includes a third conductive path and a fourth conductive path configured to carry a second pair of differential signals representative of a quadrature signal corresponding to the in-phase signal. The first and second conductive paths are in a conductive layer of the semiconductor structure, and the third and fourth conductive paths are in another conductive layer of the semiconductor structure.

Claims

1. A semiconductor structure comprising:

a first conductive path and a second conductive path configured to carry a first pair of differential signals representative of an in-phase signal;

a third conductive path and a fourth conductive path configured to carry a second pair of differential signals representative of a quadrature signal corresponding to the in-phase signal;

a first dummy conductive path; and

a second dummy conductive path, wherein the first conductive path, the second conductive path, the third conductive path, and the fourth conductive path are between the first dummy conductive path and the second dummy conductive path,

wherein the first and second conductive paths are in a conductive layer of the semiconductor structure, and the third and fourth conductive paths are in another conductive layer of the semiconductor structure.

2. The semiconductor structure of claim 1, wherein the first, second, third, and fourth conductive paths extend along a first direction and are arranged according to an order, along a second direction perpendicular to the first direction, of the first, third, second, and fourth conductive paths, the first and second conductive paths are separated from the third and fourth conductive paths by an overall vertical distance.

3. The semiconductor structure of claim 1, wherein:

the first conductive path includes a first set of segments;

the second conductive path includes a second set of segments;

the third conductive path includes a third set of segments; and

the fourth conductive path includes a fourth set of segments,

corresponding segments of the first and third sets of segments being in two conductive layers, and corresponding segments of the second and fourth sets of segments being in the two conductive layers.

4. The semiconductor structure of claim 1, wherein the first conductive path is electrically isolated from the second conductive path, the third conductive path and the fourth conductive path.

5. The semiconductor structure of claim 3, wherein the corresponding segments of the second and third sets of segments are in different ones of the two conductive layers.

6. A semiconductor structure comprising:

a first conductive path, a second conductive path, a third conductive path, and a fourth conductive path;

a first dummy conductive path; and

a second dummy conductive path, wherein the first dummy conductive path is electrically connected to the second dummy conductive path by a via plug located between the first dummy conductive path and the second dummy conductive path,

wherein the first, second, third, and fourth conductive paths extend along a first direction and are arranged according to an order, along a second direction perpendicular to the first direction, of the first, third, second, and fourth conductive paths, the first and second conductive paths are separated from the third and fourth conductive paths by an overall vertical distance; and

wherein the first and second conductive paths are in a conductive layer of the semiconductor structure, and the third and fourth conductive paths are in another conductive layer of the semiconductor structure.

7. The semiconductor structure of claim 6, wherein the first conductive path and the second conductive path are configured to carry a first pair of differential signals representative of an in-phase signal;

and

the third conductive path and the fourth conductive path configured to carry a second pair of differential signals representative of a quadrature signal corresponding to the in-phase signal.

8. The semiconductor structure of claim 6, wherein:

the first conductive path includes a first set of segments;

the second conductive path includes a second set of segments;

the third conductive path includes a third set of segments; and

the fourth conductive path includes a fourth set of segments,

corresponding segments of the first and third sets of segments being in two conductive layers, and corresponding segments of the second and fourth sets of segments being in the two conductive layers.

9. The semiconductor structure of claim 6, further comprising a third dummy conductive path, wherein the first conductive path, the second conductive path, the third conductive path and the fourth conductive path are between the first dummy conductive path and the third dummy conductive path, and the first conductive path is electrically isolated from the second conductive path, the third conductive path and the fourth conductive path.

10. The semiconductor structure of claim 8, wherein the corresponding segments of the second and third sets of segments are in different ones of the two conductive layers.

11. A semiconductor structure comprising:

a first conductive path and a second conductive path configured to carry a first pair of differential signals representative of an in-phase signal;

a third conductive path and a fourth conductive path configured to carry a second pair of differential signals representative of a quadrature signal corresponding to the in-phase signal;

a first dummy conductive path, wherein the first dummy conductive path is on a same conductive layer as the first conductive path; and

a second dummy conductive path, wherein the second dummy conductive path is on a same conductive layer as the third conductive path,

wherein the first, second, third, and fourth conductive paths extend along a first direction and are arranged according to an order, along a second direction perpendicular to the first direction, of the first, third, second, and fourth conductive paths, the first and second conductive paths are separated from the third and fourth conductive paths by an overall vertical distance.

12. The semiconductor structure of claim 11, wherein the first and second conductive paths are in a plurality of first conductive layers of the semiconductor structure, and the third and fourth conductive paths are in a plurality of second conductive layers of the semiconductor structure lower than the plurality of the first conductive layers.

13. The semiconductor structure of claim 11, wherein the first and second conductive paths are in a plurality of first conductive layers of the semiconductor structure, the third and fourth conductive paths are in a plurality of second conductive layers of the semiconductor structure interleaved with the plurality of the first conductive layers.

14. The semiconductor structure of claim 11, wherein:

the first conductive path includes a first set of segments;

the second conductive path includes a second set of segments;

the third conductive path includes a third set of segments; and

the fourth conductive path includes a fourth set of segments,

corresponding segments of the first and third sets of segments being in two conductive layers, and corresponding segments of the second and fourth sets of segments being in the two conductive layers.

15. The semiconductor structure of claim 11, wherein the first conductive path is electrically isolated from the second conductive path, the third conductive path and the fourth conductive path.

16. The semiconductor structure of claim 14, wherein the corresponding segments of the second and third sets of segments are in different ones of the two conductive layers.

17. The semiconductor structure of claim 14, wherein all segments of the first, second, third, and fourth sets of segments have a same predetermined segment length.

18. The semiconductor structure of claim 14, wherein all segments of the first, second, third, and fourth sets of segments have either a first predetermined segment length or a second predetermined segment length, and any two consecutive segments of the all segments have different segment lengths.

19. The semiconductor structure of claim 14, further comprising:

a third dummy conductive path and a fourth dummy conductive path in the other one of the two conductive layers and extending along the first direction, the first, second, third, and fourth conductive paths being horizontally between the third dummy conductive path and the fourth dummy conductive path.

20. The semiconductor structure of claim 19, wherein the first and third dummy conductive paths are positioned one over the other and connected by a plurality of via plugs, and the second and fourth dummy conductive paths are positioned one over the other and connected by another plurality of via plugs.