Methods of forming 3-D circuits with integrated passive devices

• US 9,698,131 B2
• Filed: 12/21/2015
• Issued: 07/04/2017
• Est. Priority Date: 11/25/2008
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Jones, Robert E., Sanders, Paul W., Petras, Michael F., Ramiah, Chandrasekaram
• Primary Examiner(s): FERNANDES, ERROL V
• Application Number:
  US14/977,214
• Publication Number:
  US 20160111404A1
• Time in Patent Office: 561 Days
• Field of Search: 257621, 257659, 257686, 257692, 257700, 257724, 257774, 257778, 438107, 438667
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16503 comprising an intermetallic compound
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81203 Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/81894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/83365 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/83385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/3675 : characterised by the shape of the housing
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/58 : Structural electrical arrangements for semiconductor devices not otherwise provided for , e.g. in combination with batteries H01L23/49593, H01L23/49596 take precedence
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/162 : the devices being mounted on two or more different substrates
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0296 : involving a specific disposition of the protective devices
• CPC Class Codes: H01L 27/0629 : in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/00 : Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01021 : Scandium [Sc]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrates-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so the TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.

Claims

1. A structure comprising circuitry for operation at one or more frequencies at least as high as a radio frequency, the circuitry comprising:

one or more active devices; and

one or more passive devices electrically coupled to the one or more active devices;

wherein the structure comprises;

a first semiconductor substrate comprising at least part of the one or more active devices;

a second semiconductor substrate overlying the first semiconductor substrate and supporting at least part of the one or more passive devices located over the second semiconductor substrate; and

a third semiconductor substrate located between the first and second semiconductor substrates;

wherein the circuitry further comprises one or more conductive paths passing through the second and third semiconductor substrates and electrically coupling the one or more passive devices to the one or more active devices;

wherein the third semiconductor substrate is a semiconductor material reducing electromagnetic coupling between the one or more passive devices and the one or more active devices at least at one of the one or more frequencies; and

wherein the second semiconductor substrate is a semiconductor material reducing electromagnetic coupling between the one or more passive devices and the one or more active devices at least at one of the one or more frequencies.

2. The structure of claim 1 wherein:

said at least part of the one or more active devices is spaced from a bottom of the first semiconductor substrate; and

the structure further comprises a heat sink attached to the bottom of the first semiconductor substrate.

3. The structure of claim 2 wherein the first semiconductor substrate is two or more times thinner than each of the second and third semiconductor substrates.

4. The structure of claim 1 wherein:

said at least part of the one or more active devices is located at a top of the first semiconductor substrate; and

the first semiconductor substrate is two or more times thinner than each of the second and third semiconductor substrates.

5. The structure of claim 4 further comprising a heat sink attached to a bottom of the first semiconductor substrate.

6. The structure of claim 1 wherein the circuitry is a power amplifier for operation at said one or more frequencies.

7. The structure of claim 1 wherein at least one said passive device comprises an element operating as a transmission line at least at one of the one or more frequencies, the transmission line comprising a first conductive strip and a second conductive strip, the first conductive strip overlying the second semiconductor substrate, the second conductive strip being between the second and third semiconductor substrates.

8. The structure of claim 1 wherein at least one said device comprises a first conductive strip and a second conductive strip, the first conductive strip overlying the second semiconductor substrate, the second conductive strip being between the second and third semiconductor substrates, the first and second conductive strips being a differential signal pair.

9. The structure of claim 1 wherein at least one said passive device comprises one or more inductor loops overlying the second semiconductor substrate.

10. The structure of claim 9 wherein said at least one said passive device comprising the one or more inductor loops also comprises a ground plane between the second and third semiconductor substrates, the ground plane being patterned, the ground plane being for reducing eddy current losses at least at one of the one or more frequencies.

11. The structure of claim 1 further comprising an electromagnetic band gap structure located between the second and third semiconductor substrates to enhance shielding of the first semiconductor substrate and said at least part of the one or more active devices from said at least part of the one or more passive devices at least at one of the one or more frequencies.

12. The structure of claim 1 wherein the semiconductor material of the third semiconductor substrate is at least as effective as a silicon material having a resistivity of at least 1000 ohm-cm in reducing the electromagnetic coupling between the one or more passive devices and the one or more active devices at least at said corresponding one of the one or more frequencies.

13. The structure of claim 1 wherein the semiconductor material of the second semiconductor substrate is at least as effective as a silicon material having a resistivity of at least 1000 ohm-cm in reducing the electromagnetic coupling between the one or more passive devices and the one or more active devices at least at said corresponding one of the one or more frequencies.

14. A method comprising operating, at one or more frequencies which are at least as high as a radio frequency, a circuitry comprising:

one or more active devices; and

one or more passive devices electrically coupled to the one or more active devices;

wherein at least part of the one or more active devices is located in a first semiconductor substrate;

at least part of the one or more passive devices is located over a second semiconductor substrate overlying the first semiconductor substrate; and

a third semiconductor substrate is located between the first and second semiconductor substrates;

wherein the circuitry comprises one or more conductive paths passing through the second and third semiconductor substrates and electrically coupling the one or more passive devices to the one or more active devices;

wherein the third semiconductor substrate is a semiconductor material reducing electromagnetic coupling between the one or more passive devices and the one or more active devices at least at one of the one or more frequencies; and

wherein the second semiconductor substrate is a semiconductor material reducing electromagnetic coupling between the one or more passive devices and the one or more active devices at least at one of the one or more frequencies.

15. The method of claim 14 wherein:

said at least part of the one or more active devices is spaced from a bottom of the first semiconductor substrate; and

a heat sink is attached to the bottom of the first semiconductor substrate.

16. The method of claim 15 wherein the first semiconductor substrate is two or more times thinner than each of the second and third semiconductor substrates.

17. The method of claim 14 wherein:

said at least part of the one or more active devices is located at a top of the first semiconductor substrate; and

the first semiconductor substrate is two or more times thinner than each of the second and third semiconductor substrates.

18. The method of claim 14 wherein the circuitry is a power amplifier.

19. The method of claim 14 wherein at least one said passive device comprises a transmission line comprising a first conductive strip and a second conductive strip, the first conductive strip overlying the second semiconductor substrate, the second conductive strip being between the second and third semiconductor substrates.

20. The method of claim 14 wherein at least one said device comprises a first conductive strip and a second conductive strip, the first conductive strip overlying the second semiconductor substrate, the second conductive strip being between the second and third semiconductor substrates, the first and second conductive strips being a differential signal pair.

21. The method of claim 14 wherein at least one said passive device comprises one or more inductor loops overlying the second semiconductor substrate, and also comprises a patterned ground plane between the second and third semiconductor substrates, the ground plane reducing eddy current losses.

22. The method of claim 14 further comprising an electromagnetic band gap structure located between the second and third semiconductor substrates and enhancing shielding of the first semiconductor substrate and said at least part of the one or more active devices from said at least part of the one or more passive devices.

23. The method of claim 14 wherein the semiconductor material of the third semiconductor substrate is at least as effective as a silicon material having a resistivity of at least 1000 ohm-cm in reducing the electromagnetic coupling between the one or more passive devices and the one or more active devices at least at said corresponding one of the one or more frequencies.

24. The method of claim 14 wherein the semiconductor material of the second semiconductor substrate is at least as effective as a silicon material having a resistivity of at least 1000 ohm-cm in reducing the electromagnetic coupling between the one or more passive devices and the one or more active devices at least at said corresponding one of the one or more frequencies.