Transistor device with field-electrode

• US 9,698,228 B2
• Filed: 12/21/2015
• Issued: 07/04/2017
• Est. Priority Date: 12/22/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Kampen, Christian, Zundel, Markus
• Primary Examiner(s): YEUNG LOPEZ, FEIFEI
• Application Number:
  US14/976,604
• Publication Number:
  US 20160181417A1
• Time in Patent Office: 561 Days
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Disclosed is a transistor device. The transistor device includes a plurality of field structures which define a plurality of semiconductor mesa regions in a semiconductor body, and each of which comprises a field electrode and a field electrode dielectric; a plurality of gate structures in each semiconductor mesa region, wherein each gate structure comprises a gate electrode and a gate dielectric, and is arranged in a trench of the semiconductor mesa region; a plurality of body regions, a plurality of source regions, and a drift region. Each body region adjoins the gate dielectric of at least one of the plurality of gate structures, and is located between one of the plurality of source regions and the drift region.

Claims

1. A transistor device, comprising:

a plurality of field structures that define a plurality of semiconductor mesa regions in a semiconductor body, and each of which comprises a field electrode and a field electrode dielectric;

a plurality of gate structures in each semiconductor mesa region, wherein each gate structure comprises a gate electrode and a gate dielectric, and is arranged in a trench of the semiconductor mesa region; and

a plurality of body regions, a plurality of source regions, and a drift region,

wherein each body region adjoins the gate dielectric of at least one of the plurality of gate structures, and is located between one of the plurality of source regions and the drift region,

wherein the plurality of body regions comprises a first group of body regions and a second group of body regions,

wherein each body region of the first group is located between two neighboring gate structures of the plurality of gate structures,

wherein each body region of the second group is located between one of the plurality of gate structures and one of the plurality of field structures, and

wherein a width of each of the body regions of the second group is less than the width of one body region of the first group.

2. The transistor device of claim 1, further comprising a drain region, wherein the drift region is arranged between the plurality of body regions and the drain region.

3. The transistor device of claim 1, wherein the drift region is at least partially arranged in the plurality of mesa regions.

4. The transistor device of claim 3, wherein the drift region adjoins the field electrode dielectric of two neighboring field structures in each mesa region.

5. The transistor device of claim 1, further comprising:

a gate node electrically connected to each of the plurality of gate electrodes;

a source node electrically connected to each of the plurality of source regions; and

a drain node electrically connected to a drain region.

6. The transistor device of claim 5, wherein each of the plurality of field electrodes is connected to the source node.

7. The transistor device of claim 5, wherein each of the plurality of field electrodes is connected to the gate node.

8. The transistor device of claim 1, wherein each semiconductor mesa region comprises two or more gate structures.

9. The transistor of claim 1,

wherein a ratio between a first width of each of the body regions of the first group and a length of one body region in a current flow direction is less than 1, less than 0.5, or less than 0.3.

10. The transistor of claim 1,

wherein a width of each of the body regions of the second group is 50% of the width of one body region of the first group.

11. The transistor of claim 1,

wherein the plurality of body regions comprises a first group of body regions,

wherein each body region of the first group is located between two neighboring gate structures of the plurality of gate structures, and

wherein a first width of each of the body regions of the first group is less than 200 nm.

12. The transistor device of claim 1, further comprising:

a gate electrode that is arranged in at least one of the field electrode structures, and that is adjacent and dielectrically insulated from one of the plurality of body regions.

13. The transistor device of claim 1, wherein a width of each of the plurality of mesa regions is between 200 nm and 2000 nm.

14. The transistor device of claim 1, wherein the field structures of the plurality of field structures are elongated structures which are substantially parallel in a horizontal plane of the semiconductor body.

15. The transistor device of claim 1, wherein the field structures of the plurality of field structures form a grid-shaped structure in a horizontal plane of the semiconductor body.

16. The transistor device of claim 1, wherein the gate structures of the plurality of gate structures in each of the plurality of semiconductor mesa regions are substantially parallel in a horizontal plane of the semiconductor body.

17. A transistor device, comprising:

a plurality of field structures that define a plurality of semiconductor mesa regions in a semiconductor body, and each of which comprises a field electrode and a field electrode dielectric;

a plurality of gate structures in each semiconductor mesa region, wherein each gate structure comprises a gate electrode and a gate dielectric, and is arranged in a trench of the semiconductor mesa region; and

a plurality of body regions, a plurality of source regions, and a drift region,

wherein each body region adjoins the gate dielectric of at least one of the plurality of gate structures, and is located between one of the plurality of source regions and the drift region;

wherein the plurality of body regions comprises a first group of body regions and a second group of body regions,

wherein each body region of the first group is located between two neighboring gate structures of the plurality of gate structures,

wherein each body region of the second group is located between one of the plurality of gate structures and one of the plurality of field structures, and

wherein a ratio between a width of each of the body regions of the second group and a length of one body region in a current flow direction is less than 0.5.

18. The transistor of claim 17, wherein a width of each of the body regions of the second group is less than the width of one body region of the first group.

19. The transistor of claim 17, wherein a ratio between a first width of each of the body regions of the first group and a length of one body region in a current flow direction is less than 1, less than 0.5, or less than 0.3.

20. The transistor of claim 17, wherein a width of each of the body regions of the second group is 50% of the width of one body region of the first group.