Power MOS transistor and manufacturing method therefor

• US 9,698,248 B2
• Filed: 08/04/2014
• Issued: 07/04/2017
• Est. Priority Date: 07/25/2014
• Status: Active Grant

• Current Assignee: Suzhou Oriental Semiconductor Co., Ltd.
• Original Assignee: Suzhou Oriental Semiconductor Co., Ltd.
• Inventors: Liu, Wei, Liu, Lei, Lin, Xi, Wang, Pengfei, Gong, Yi
• Primary Examiner(s): Nguyen, Cuong B
• Application Number:
  US15/028,718
• Publication Number:
  US 20160276464A1
• Time in Patent Office: 1,065 Days
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/32 using masks
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/157 Doping structures, e.g. doping superlattices, nipi superlattices delta doping in general H01L29/365
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The present invention discloses a power Metal Oxide Semiconductor (MOS) transistor, wherein a second U-shaped trench is formed below a first U-shaped trench, so that a field oxidation stress transition region can be extended, so as to greatly reduce current leakage caused by the field oxidation stress and improve the reliability of the device; and a charge compensation region is provided in a drift region at the bottom of the second U-shaped trench, and a super-junction structure is formed between the charge compensation region and the drift region to improve the breakdown voltage of the power device. According to the present invention, the second U-shaped trench and the charge compensation region are formed by a self-aligning process, so that the technical process is simple, reliable and easy to control, and can reduce the manufacturing cost of the power MOS transistor and improve its yield.

Claims

1. A power Metal Oxide Semiconductor (MOS) transistor, comprising:

a drain region of a first doping type in a semiconductor substrate, a drift region of the first doping type, a channel region of a second doping type, a source region of the first doping type and a first U-shaped trench, wherein the drain region is provided at a bottom of the semiconductor substrate, the drift region is provided above the drain region, the channel region is provided on both sides of side walls of the first U-shaped trench and above die drift region, a bottom of the first U-shaped trench extends into the drift region, a gate oxide layer covering the channel region is provided on, and the source region is provided at a top of the semiconductor substrate and above the channel region;

a channel region contact region is provided in the channel region, the doping type of the channel region contact region is die same as that of the channel region, and a doping concentration of the channel region contact region is greater than that of the channel region;

a second U-shaped trench in the semiconductor substrate, wherein the second U-shaped trench is provided below the first U-shaped trench, a opening width of the second U-shaped trench is smaller than that of the first U-shaped trench, and a depth of the second U-shaped trench is 10-100 nm;

a field oxide layer is provided hi the second U-shaped trench, a thickness of the field oxide layer is greater than that of the gate oxide layer, a charge compensation region is provided in the drift region below the field oxide layer, and the charge compensation region has the second doping type, the second U-shaped trench extends a field oxide stress transition region between the field oxide layer and the gate oxide layer, and a thickness of a bottom portion of the field oxide layer is thicker than a thickness of side portions of the field oxide layer; and

a polysilicon gate covering the gate oxide layer and the field oxide layer is provided in the first U-shaped trench and the second U-shaped trench.

2. The power MOS transistor of claim 1, wherein the channel region contact region is provided at the top of the semiconductor substrate and is adjacent to the source region, or the channel region contact region is recessed in the semiconductor substrate.

3. The power MOS transistor of claim 1, wherein an upper surface of the polysilicon gate is lower than an opening surface of the first U-shaped trench, and an insulating layer is provided above the polysilicon gate and at the top of the first U-shaped trench.

4. The power MOS transistor of claim 1, wherein the first doping type is n-type doping, and the second doping type is p-type doping;

or, the first doping type is p-type doping, and the second doping type is n-type doping.