Ultra low voltage ring oscillator with redundant inverter

• US 9,698,763 B1
• Filed: 12/31/2015
• Issued: 07/04/2017
• Est. Priority Date: 12/31/2015
• Status: Active Grant

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: Lau, Benjamin Shui Chor, Heng, Chun Huat, Luo, Zhihong, Lian, Yong
• Primary Examiner(s): Kinkead, Arnold
• Application Number:
  US14/985,457
• Publication Number:
  US 20170194948A1
• Time in Patent Office: 551 Days
• Field of Search: 331 57, 327261, 327291
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 5/133 using a chain of active delay devices

Abstract

Redundant inverters with multiple inverter stages enable lower operating voltages to be used. For example, the use of multiple inverter stages produces a strong “0” or a strong “1” output signal. The strong output signal facilitates self-oscillation of a ring oscillator at lower voltages.

Claims

1. A redundant inverter comprising:

a redundant inverter input terminal for receiving an inverter input signal;

a redundant inverter output terminal for generating an inverter output signal;

an input module, the input module includes

a high section which includes a first input inverter having a first p-type transistor and a first n-type transistor coupled in series between a first input inverter high power source and a first input inverter low power source, the first input inverter includes a first inverter input terminal coupled to the redundant inverter input terminal and a first inverter output terminal which serves as a high section output terminal, and

a low section with a second input inverter having a second p-type transistor and a second n-type transistor coupled in series between a second input inverter high and low power sources, the second input inverter includes a second inverter input terminal coupled to the redundant inverter input terminal and a second inverter output terminal which serves as a low section output terminal; and

an output module with an output inverter, the output inverter includes

an output p-type transistor and an output n-type transistor coupled in series between the first inverter output terminal and the second inverter output terminal,

a first output inverter terminal coupled to the redundant inverter output terminal, and

a second output inverter terminal coupled to the redundant inverter input terminal.

2. The redundant inverter of claim 1 wherein:

in response to a logic 1 input signal at the redundant inverter input terminal,

the first input inverter of the high section is configured to generate a weak “

0”

at the high section output terminal, and

the second input inverter of the low section is configured to generate a strong “

0”

at the low section output terminal; and

in response to a logic 0 input signal at the redundant inverter input terminal,

the first inverter of the high section is configured to generate a strong “

1”

at the high section output terminal, and

the second inverter of the low section is configured to generate a weak “

1”

at the low section output terminal.

3. The redundant inverter of claim 2 wherein:

the redundant inverter output terminal comprises a strong “

1”

in response to a logic 0 input signal at the redundant inverter input terminal; and

the redundant inverter output terminal comprises a strong “

0”

in response to a logic 1 input signal at the redundant inverter input terminal.

4. The redundant inverter of claim 1 wherein:

the input module comprises a single input stage; and

the input module and the output module form a 2-stage redundant inverter.

5. The redundant inverter of claim 1 wherein:

the first and second input inverters form a single stage input module;

the first and second high power sources comprise device high power sources;

the first and second low power sources comprise device low power sources, and

the single stage input module and output module form a 2-stage redundant inverter.

6. The redundant inverter of claim 5 wherein:

in response to a logic 1 input signal at the redundant inverter input terminal,

the first input inverter of the high section is configured to generate a weak “

0”

at the high section output terminal, and

the second input inverter of the low section is configured to generate a strong “

0”

at the low section output terminal; and

in response to a logic 0 input signal at the redundant inverter input terminal,

the first inverter of the high section is configured to generate a strong “

1”

at the high section output terminal, and

the second inverter of the low section is configured to generate a weak “

1”

at the low section output terminal.

7. The redundant inverter of claim 6 wherein:

the first p-type transistor of the first input inverter is a large pFET;

the first n-type transistor of the first input inverter is a small nFET;

the second p-type transistor of the second input inverter is a small pFET; and

the second n-type transistor of the second input inverter is a large nFET.

8. The redundant inverter of claim 1 is incorporated in a ring oscillator circuit comprising a plurality of redundant inverters connected in series, wherein a last of the redundant inverter is series connected to a first of the redundant inverter to form a ring.

9. The redundant inverter of claim 1 wherein the input module comprises first and second input stages to form a 3-stage redundant inverter, wherein:

the first input stage comprises the first and second input inverters;

the second stage comprises

third and fourth input inverters for the high section of the input module, wherein

the third input inverter includes a third p-type transistor and a third n-type transistor coupled in series between device high and low power sources, an input terminal of the third inverter is coupled to the redundant inverter input terminal, and an output terminal of the third inverter is coupled to the first input inverter high power source,

the fourth input inverter includes a fourth p-type transistor and a fourth n-type transistor coupled in series between device high and low power sources, an input terminal of the fourth inverter is coupled to the redundant inverter input terminal and an output terminal of the fourth inverter is coupled to the first input inverter low power source, and

fifth and sixth input inverters for the low section of the input module, wherein

the fifth input inverter includes a fifth p-type transistor and a fifth n-type transistor coupled in series between device high and low power sources, an input terminal of the fifth inverter is coupled to the redundant inverter input terminal, and an output terminal of the fifth inverter is coupled to the second input inverter high power source, and

the sixth input inverter includes a sixth p-type transistor and a sixth n-type transistor coupled in series between device high and low power sources, an input terminal of the sixth inverter is coupled to the redundant inverter input terminal, an output terminal of the sixth inverter is coupled to the second input inverter low power source.

10. The redundant inverter of claim 9 wherein:

in response to a logic 1 input signal at the redundant inverter input terminal,

the high section of the input module is configured to generate a weak “

0”

at the high section output terminal, and

the low section of the input module is configured to generate a strong “

0”

at the low section output terminal; and

in response to a logic 0 input signal at the redundant inverter input terminal,

the high section of the input module is configured to generate a strong “

1”

at the high section output terminal, and

the low section of the input module is configured to generate a weak “

1”

at the low section output terminal.

11. The redundant inverter of claim 9 wherein:

the first and second input inverters comprise balanced first and second input inverters with large FETs;

the third inverter comprises an imbalanced third inverter with a large pFET and small nFET;

the fourth and fifth input inverters comprise balanced fourth and fifth input inverters with intermediate FETs; and

the sixth inverter comprises an imbalanced sixth inverter with a small pFET and a large nFET.

12. The redundant inverter of claim 11 wherein:

in response to a logic 1 input signal at the redundant inverter input terminal,

the high section of the input module is configured to generate a weak “

0”

at the high section output terminal, and

the low section of the input module is configured to generate a strong “

0”

at the low section output terminal; and

in response to a logic 0 input signal at the redundant inverter input terminal,

the high section of the input module is configured to generate a strong “

1”

at the high section output terminal, and

the low section of the input module is configured to generate a weak “

1”

at the low section output terminal.

13. The redundant inverter of claim 12 wherein the output inverter comprises balanced output inverters with large FETs.

14. The redundant inverter of claim 13 wherein:

the redundant inverter output terminal comprises a strong “

1”

in response to a logic 0 at the redundant inverter input terminal; and

the redundant inverter output terminal comprises a strong “

0”

in response to a logic 1 at the redundant inverter input terminal.

15. The redundant inverter of claim 14 is incorporated in a ring oscillator circuit comprising a plurality of redundant inverters connected in series, wherein a last of the redundant inverter is series connected to a first of the redundant inverter to form a ring.

16. A redundant inverter comprising:

a redundant inverter input terminal for receiving an inverter input signal;

a redundant inverter output terminal for generating an inverter output signal;

an input module, the input module includes inverters arranged into

a high section generating a high section output signal at a high section output terminal,

a low section generating a low section output signal at a low section output terminal, and

wherein

in response to a logic 1 input signal at the redundant inverter input terminal,

the high section is configured to generate a weak “

0”

at the high section output terminal, and

the low section is configured to generate a strong “

0”

at the low section output terminal, and

in response to a logic 0 input signal at the redundant inverter input terminal,

the high section is configured to generate a strong “

1”

at the high section output terminal, and

the low section is configured to generate a weak “

1”

at the low section output terminal;

an output module with an output inverter, the output inverter includes

an output inverter high power source terminal coupled to the high section output terminal,

an output inverter low power source terminal coupled to the low section output terminal,

an output inverter input terminal coupled to the redundant inverter input terminal, and

an output inverter output terminal coupled to the redundant inverter output terminal.

17. The redundant inverter of claim 16 wherein the input module comprises n stages to form an n+1 stage redundant inverter, the input module comprises a sum of 2ⁱ transistors where i is from 1 to n and an i^th stage comprises 2ⁱ transistors.

18. The redundant inverter of claim 17 wherein:

an output of a first transistor of the first input stage (i=1) is the high section output terminal;

an output of a second transistor of the first input stage is the low section output terminal;

inverters of the last input stage (i=n) have transistors coupled between device high and low power sources; and

output terminals of inverters of stages from 2 to n serve as power sources for inverters of a preceding stage (i=i−

1).

19. The redundant inverter of claim 16 is incorporated in a ring oscillator circuit comprising a plurality of redundant inverters connected in series, wherein a last of the redundant inverter is series connected to a first of the redundant inverter to form a ring.

20. A ring oscillator circuit comprising a ring oscillator module having a plurality of redundant inverters connected in series to form a ring configuration, wherein a last of the redundant inverter is series connected to a first of the redundant inverter to form a ring, wherein each redundant inverter comprises:

a redundant inverter input terminal for receiving an inverter input signal;

a redundant inverter output terminal for generating an inverter output signal;

an input module, the input module includes inverters arranged into

a high section generating a high section output signal at a high section output terminal,

a low section generating a low section output signal at a low section output terminal, and

wherein

in response to a logic 1 input signal at the redundant inverter input terminal,

the high section is configured to generate a weak “

0”

at the high section output terminal, and

the low section is configured to generate a strong “

0”

at the low section output terminal, and

in response to a logic 0 input signal at the redundant inverter input terminal,

the high section is configured to generate a strong “

1”

at the high section output terminal, and

the low section is configured to generate a weak “

1”

at the low section output terminal;

an output module with an output inverter, the output inverter includes

an output inverter high power source terminal coupled to the high section output terminal,

an output inverter low power source terminal coupled to the low section output terminal,

an output inverter input terminal coupled to the redundant inverter input terminal, and

an output inverter output terminal coupled to the redundant inverter output terminal.