Digital signal up-converting apparatus and related digital signal up-converting method
First Claim
1. A digital signal up-converting apparatus, comprising:
- a clock generating circuit, arranged to generate a first reference clock signal, a second reference clock signal, a third reference clock signal, and a fourth reference clock signal;
a phase adjusting circuit, arranged to adjust the first reference clock signal, the second reference clock signal, the third reference clock signal, and the fourth reference clock signal to generate a first adjusted clock signal, a second adjusted clock signal, a third adjusted clock signal, and a fourth adjusted clock signal;
a baseband circuit, arranged to generate a first digital output signal, a second digital output signal, a third digital output signal, and a fourth digital output signal according to a first baseband data, a second baseband data, the first adjusted clock signal, the second adjusted clock signal, the third adjusted clock signal, and the fourth adjusted clock signal; and
a sampling circuit, arranged to sample the first digital output signal, the second digital output signal, the third digital output signal, and the fourth digital output signal to generate a first sampled digital signal, a second sampled digital signal, a third sampled digital signal, and a fourth sampled digital signal according to a first sampling clock signal, a second sampling clock signal, a third sampling clock signal, and a fourth sampling clock signal, respectively.
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Abstract
A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.
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Citations
21 Claims
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1. A digital signal up-converting apparatus, comprising:
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a clock generating circuit, arranged to generate a first reference clock signal, a second reference clock signal, a third reference clock signal, and a fourth reference clock signal; a phase adjusting circuit, arranged to adjust the first reference clock signal, the second reference clock signal, the third reference clock signal, and the fourth reference clock signal to generate a first adjusted clock signal, a second adjusted clock signal, a third adjusted clock signal, and a fourth adjusted clock signal; a baseband circuit, arranged to generate a first digital output signal, a second digital output signal, a third digital output signal, and a fourth digital output signal according to a first baseband data, a second baseband data, the first adjusted clock signal, the second adjusted clock signal, the third adjusted clock signal, and the fourth adjusted clock signal; and a sampling circuit, arranged to sample the first digital output signal, the second digital output signal, the third digital output signal, and the fourth digital output signal to generate a first sampled digital signal, a second sampled digital signal, a third sampled digital signal, and a fourth sampled digital signal according to a first sampling clock signal, a second sampling clock signal, a third sampling clock signal, and a fourth sampling clock signal, respectively. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A digital signal up-converting method, comprising:
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generating a first reference clock signal, a second reference clock signal, a third reference clock signal, and a fourth reference clock signal; adjusting the first reference clock signal, the second reference clock signal, the third reference clock signal, and the fourth reference clock signal to generate a first adjusted clock signal, a second adjusted clock signal, a third adjusted clock signal, and a fourth adjusted clock signal; generating a first digital output signal, a second digital output signal, a third digital output signal, and a fourth digital output signal according to a first baseband data, a second baseband data, the first adjusted clock signal, the second adjusted clock signal, the third adjusted clock signal, and the fourth adjusted clock signal; and sampling the first digital output signal, the second digital output signal, the third digital output signal, and the fourth digital output signal to generate a first sampled digital signal, a second sampled digital signal, a third sampled digital signal, and a fourth sampled digital signal according to a first sampling clock signal, a second sampling clock signal, a third sampling clock signal, and a fourth sampling clock signal, respectively. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21)
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Specification