Integrated low voltage differential signaling (LVDS) and high-speed current steering logic (HCSL) circuit and method of use

• US 9,698,787 B1
• Filed: 03/28/2016
• Issued: 07/04/2017
• Est. Priority Date: 03/28/2016
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Agrawal, Vikas, Qiu, Feng, Hsu, John C.
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Chen, Patrick
• Application Number:
  US15/083,068
• Time in Patent Office: 463 Days
• Field of Search: 327108
• CPC Class Codes: H03K 19/018514 with at least one differential stage H03K19/018528 and H03K19/018542 take precedence
• CPC Class Codes: H03K 19/018528 with at least one differential stage

Abstract

An integrated circuit includes a low voltage differential signaling (LVDS) output circuit, a high-speed current steering logic (HCSL) output circuit, a bias control circuit, a programmable voltage reference circuit coupled to the bias control circuit, an output stage circuit coupled to the HCSL output circuit, a first plurality of switches to switchably couple the bias control circuit to the LVDS output circuit, a second plurality of switches to switchably couple the bias control circuit to the output stage circuit and to the HCSL output circuit and a logic control circuit coupled to the programmable voltage reference circuit, the first plurality of switches and the second plurality of switches. The logic control circuit is configured to activate either the LVDS output circuit or the HCSL output circuit.

Claims

1. An integrated circuit comprising:

a low voltage differential signaling (LVDS) output circuit;

a high-speed current steering logic (HCSL) output circuit;

a bias control circuit;

a programmable voltage reference circuit coupled to the bias control circuit;

an output stage circuit coupled to the HCSL output circuit;

a first plurality of switches to switchably couple the bias control circuit to the LVDS output circuit; and

a second plurality of switches to switchably couple the bias control circuit to the output stage circuit and to the HCSL output circuit.

2. The integrated circuit of claim 1, further comprising a logic control circuit coupled to the programmable voltage reference circuit, the first plurality of switches and the second plurality of switches, the logic control circuit to activate either the LVDS output circuit or the HCSL output circuit.

3. The integrated circuit of claim 2 wherein the HCSL output circuit further comprises:

a second pre-driver and power down logic circuit;

a push-pull voltage logic stage coupled to the second pre-driver and power down logic circuit, the push-pull voltage logic stage to provide a differential output signal; and

a first n-channel metal oxide semiconductor (NMOS) device having a gate coupled to the output stage circuit, a drain coupled to a differential output power supply and a source coupled to the push-pull voltage logic stage.

4. The integrated circuit of claim 3, wherein the second pre-driver and power down logic circuit provides a true output signal and a complimentary output signal and wherein the push-pull voltage logic stage further comprises a first pair of n-channel metal oxide semiconductor (NMOS) devices coupled to the true output signal and a second pair of n-channel metal oxide semiconductor (NMOS) devices coupled to the compliment output signal.

5. The integrated circuit of claim 1, wherein the LVDS output circuit further comprises;

a first pre-driver and power down logic circuit;

a current mode logic stage coupled to the first pre-driver and power down logic circuit, the current mode logic stage to provide a differential output signal;

a termination resistor coupled across the differential output signal of the current mode logic stage; and

a current source coupled across the current mode logic stage to drive the differential output signal across the termination resistor.

6. The integrated circuit of claim 5, wherein the first pre-driver and power down logic circuit provides a true output signal and a compliment output signal and wherein the current mode logic stage further comprises a first differential pair of metal oxide semiconductor (MOS) devices coupled to the true output signal and a second differential pair of metal oxide semiconductor (MOS) devices coupled to the compliment output signal.

7. The integrated circuit of claim 1, wherein the bias control circuit further comprises a common mode feedback amplifier circuit to define an output signaling level for the LVDS output circuit.

8. The integrated circuit of claim 1, further comprising a bandgap reference circuit coupled to the bias control circuit and the programmable voltage reference circuit.

9. The integrated circuit of claim 8, wherein the programmable voltage reference circuit further comprises a plurality of selectable resistive devices to provide a voltage reference signal to the bias control circuit based upon an input from the bandgap reference circuit and an input from a logic control circuit.

10. The integrated circuit of claim 9, wherein the input from the logic control circuit instructs the programmable voltage reference circuit to generate an appropriate voltage reference signal for an LVDS output signaling mode or for an HCSL output signaling mode.

11. The integrated circuit of claim 1, wherein the output stage circuit further comprises, a differential pair amplifier with current mirroring to define an output signaling level for the HCSL output circuit.

12. An integrated circuit comprising:

a low voltage differential signaling (LVDS) output circuit;

a high-speed current steering logic (HCSL) output circuit;

a bias control circuit;

a programmable voltage reference circuit coupled to the bias control circuit;

an output stage circuit coupled to the HCSL output circuit;

a first plurality of switches to switchably couple the bias control circuit to the LVDS output circuit;

a second plurality of switches to switchably couple the bias control circuit to the output stage circuit and to the HCSL output circuit; and

a logic control circuit coupled to the programmable voltage reference circuit, the first plurality of switches and the second plurality of switches, the logic control circuit to activate either the LVDS output circuit or the HCSL output circuit.

13. A method comprising:

providing a voltage reference signal from a programmable voltage reference circuit to a bias control circuit based upon a desired output signaling mode by providing a bandgap current reference signal from a bandgap reference circuit to the programmable voltage reference circuit and providing a control signal from a logic control circuit to the programmable voltage reference circuit, wherein the control signal is based upon the desired output signaling mode and wherein the desired output signaling mode is either a low voltage differential signaling (LVDS) output signaling mode or a high-speed current steering logic (HCSL) output signaling mode;

coupling the bias control circuit to a LVDS output circuit if the desired output signaling mode is an LVDS output signaling mode or coupling the bias control circuit to a HCSL output circuit if the desired output signaling mode is an HCSL output signaling mode; and

coupling the bias control circuit to an output stage circuit coupled to the HCSL output circuit if the desired output signaling mode is an HCSL output signaling mode.

14. The method of claim 13, wherein coupling the bias control circuit to a LVDS output circuit if the desired output signaling mode is an LVDS output signaling mode further comprises, providing a common mode voltage to the LVDS output circuit to define an output signaling level for the LVDS output circuit based upon the desired LVDS output signaling mode.

15. The method of claim 13, wherein coupling the bias control circuit to a LVDS output circuit if the desired output signaling mode is an LVDS output signaling mode further comprises, providing a common mode feedback path between the bias control circuit and the LVDS output circuit.

16. A method comprising:

providing a voltage reference signal from a programmable voltage reference circuit to a bias control circuit based upon a desired output signaling mode, wherein the desired output signaling mode is either a low voltage differential signaling (LVDS) output signaling mode or a high-speed current steering logic (HCSL) output signaling mode;

coupling the bias control circuit to a LVDS output circuit if the desired output signaling mode is an LVDS output signaling mode or coupling the bias control circuit to a HCSL output circuit by providing a common mode feedback path between the bias control circuit and the HCSL output circuit if the desired output signaling mode is an HCSL output signaling mode; and

coupling the bias control circuit to an output stage circuit coupled to the HCSL output circuit if the desired output signaling mode is an HCSL output signaling mode.

17. The method of claim 16, wherein coupling the bias control to an output stage circuit coupled to the HCSL output circuit if the desired output signaling mode is an HCSL output signaling mode further comprises, providing a common mode voltage from the output stage circuit to the HCSL output circuit to define an output signaling level for the HCSL output circuit based upon the desired HCSL output signaling mode.

18. The method of claim 16, wherein coupling the bias control circuit to a LVDS output circuit if the desired output signaling mode is an LVDS output signaling mode further comprises, closing a first plurality of switches, between the bias control circuit and the LVDS output circuit.

19. The method of claim 18, wherein coupling the bias control circuit to a HCSL output circuit if the desired output signaling mode is an HCSL output signaling mode and coupling the bias control to an output stage circuit coupled to the HCSL output circuit if the desired output signaling mode is an HCSL output signaling mode further comprises, closing a second plurality of switches between the bias control circuit and the HCSL output circuit, and between the bias control circuit and the output stage circuit.