Power amplifier open loop current clamp

• US 9,698,853 B2
• Filed: 07/07/2014
• Issued: 07/04/2017
• Est. Priority Date: 07/31/2013
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Ripley, David Steven, Andrys, Paul Raymond, Miller, Kyle James, Banowetz, Matthew Lee
• Primary Examiner(s): HUANG, WEN WU
• Application Number:
  US14/325,314
• Publication Number:
  US 20150038092A1
• Time in Patent Office: 1,093 Days
• Field of Search: 4551143, 4551271, 4551272
• CPC Class Codes: H03F 1/0233 by using a signal derived from the output signal, e.g. bootstrapping the voltage supply
• CPC Class Codes: H03F 1/52 Circuit arrangements for protecting such amplifiers monitoring arrangements G01R31/28; increasing reliability in communication systems, e.g. using redundancy H04B1/74
• CPC Class Codes: H03F 2200/426 the amplifier comprising circuitry for protection against overload
• CPC Class Codes: H03F 2200/441 Protection of an amplifier being implemented by clamping means
• CPC Class Codes: H03F 2200/462 the current being sensed
• CPC Class Codes: H03F 3/191 Tuned amplifiers H03F3/193, H03F3/195 take precedence
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04B 2001/0408 with power amplifiers

Abstract

Various implementations include circuits, devices and/or methods that provide open loop current limiting power amplifiers and the like. In some implementations, an open loop current clamp includes a trim module to provide a control value and a limiting source having respective input and output terminals. The input terminal is coupled to the trim module to receive the control value. The output terminal coupled to a control terminal of the first transistor to provide a limiting electrical level produced in response to the control value by the limiting source. The limiting electrical level substantially setting a first mode of operation for the first transistor such that the current draw of the first transistor is substantially determined by the first mode of operation and the limiting electrical level such that a voltage at an output terminal of the first transistor exerts reduced influence on the current draw.

Claims

1. An open loop current clamp to restrict the current draw of a first transistor, the open loop current clamp comprising:

a current trim module including a voltage source having a voltage output terminal to provide a reference voltage, an adjustable resistive load and a control value generator configured to provide a control value as a function of the reference voltage and a voltage drop across the adjustable resistive load; and

a limiting first current source having respective input and output terminals, the input terminal coupled to the current trim module to receive the control value, and the output terminal coupled to a first control terminal of the first transistor to provide a limiting electrical level produced in response to the control value, such that the limiting electrical level substantially sets a first mode of operation for the first transistor such that the current draw of the first transistor is substantially determined by the first mode of operation and the limiting electrical level such that a voltage at a first output terminal of the first transistor exerts reduced influence on the current draw.

2. The open loop current clamp of claim 1 further comprising a current mirror including a second transistor, the second transistor having a second control terminal and a second input terminal, the second control terminal of the second transistor coupled to the first control terminal of the first transistor, and the current mirror also including a second current source coupled to the second input terminal of the second transistor to form an input portion of the current mirror, the second current source provided to set the nominal DC current drawn by the input portion of the current mirror, and an output portion of the current mirror includes the first transistor.

3. The open loop current clamp of claim 2 further comprising a resistor and capacitor in series between the second input terminal and second control terminal of the second transistor.

4. The open loop current clamp of claim 2 wherein the first and second transistors are together characterized by a device area ratio that is used to determine in part the current drawn by the first transistor relative to the output of the second current source coupled to the second transistor.

5. The open loop current clamp of claim 2 further comprising a gain helper having first, second and third terminals, wherein the first terminal is coupled to the output of the second current source, the second terminal is coupled to the output of the limiting first current source, and the third terminal is coupled to the first control terminal of the first transistor.

6. The open loop current clamp of claim 5 wherein the gain helper is a transistor.

7. The open loop current clamp of claim 6 wherein the first and second transistors are bipolar junction transistors, the gain helper is a metal oxide semiconductor transistor, and the gain is defined as the current gain of a bipolar junction transistor.

8. The open loop current clamp of claim 1 wherein the first transistor comprises a bipolar junction transistor, and the limiting electrical level is a current provided to the base of the bipolar junction transistor.

9. The open loop current clamp of claim 1 wherein the control value is a function of the difference between the reference voltage and the voltage drop across the resistive load.

10. The open loop current clamp of claim 1 wherein the adjustable resistive load comprises:

a plurality of parallel resistors selectively connectable to a common node;

a plurality of switches coupled to selectively connect one or more of the respective resistors to the common node in order to change the effective resistance of the adjustable resistive load; and

a control bus coupled to the plurality of switches to provide respective control signals.

11. The open loop current clamp of claim 1 wherein the first transistor is a bipolar junction transistor.

12. The open loop current clamp of claim 1 wherein the first transistor is heterojunction bipolar transistor.

13. The open loop current clamp of claim 1 wherein the limiting first current source and current trim module are included on a first die that is separate from a second die including the first transistor.

14. The open loop current clamp of claim 1 wherein the limiting first current source and current trim module are included on the same die as the first transistor.

15. The open loop current clamp of claim 1 wherein the limiting first current source includes an adjustable current mirror, the adjustable current mirror comprising:

a plurality of parallel transistors selectively connectable to a common node;

a plurality of switches coupled to selectively connect one or more of the respective transistors to the common node in order set a reference current of the adjustable current mirror; and

a control bus coupled to the plurality of switches to provide respective control signals.

16. A power amplifier module comprising:

a packaging substrate configured to receive a plurality of components;

a power amplifier circuit provided in a die included on the packaging substrate, the power amplifier including a first transistor having a first control terminal and a first output terminal;

a current trim module including a voltage source having a voltage output terminal to provide a reference voltage, an adjustable resistive load and a control value generator configured to provide a control value as a function of the reference voltage and a voltage drop across the adjustable resistive load; and

a limiting first current source having respective input and output terminals, the input terminal coupled to the current trim module to receive the control value, and the output terminal coupled to the first control terminal of the first transistor to provide a limiting electrical level produced in response to the control value, such that the limiting electrical level substantially sets a first mode of operation for the first transistor such that the current draw of the first transistor is substantially determined by the first mode of operation and the limiting electrical level such that a voltage at the first output terminal of the first transistor exerts reduced influence on the current draw.

17. The power amplifier module of claim 16 wherein at least a portion of one of the current trim module and limiting first current source is provided on the same die as the power amplifier.

18. The power amplifier module of claim 17 wherein the die is a heterojunction bipolar junction transistor die.

19. A radio frequency (RF) device comprising:

a transceiver configured to process RF signals;

an antenna in communication with the transceiver configured to facilitate transmission of an amplified RF signal; and

a power amplifier module connected to the transceiver and configured to generate the amplified RF signal, the power amplifier module including a first transistor, a current trim module including a voltage source having a voltage output terminal to provide a reference voltage, an adjustable resistive load and a control value generator configured to provide a control value as a function of the reference voltage and a voltage drop across the adjustable resistive load, and a limiting first current source having respective input and output terminals, the input terminal coupled to the current trim module to receive the control value, and the output terminal coupled to a first control terminal of the first transistor to provide a limiting electrical level produced in response to the control value, such that the limiting electrical level substantially sets a first mode of operation for the first transistor such that the current draw of the first transistor is substantially determined by the first mode of operation and the limiting electrical level such that a voltage at a first output terminal of the first transistor exerts reduced influence on the current draw.

20. The radio frequency (RF) device of claim 19 wherein the adjustable resistive load comprises:

a plurality of parallel resistors selectively connectable to a common node;

a plurality of switches coupled to selectively connect one or more of the respective resistors to the common node in order to change the effective resistance of the adjustable resistive load; and

a control bus coupled to the plurality of switches to provide respective control signals.