Hybrid printed circuit assembly with low density main core and embedded high density circuit regions

• US 9,699,906 B2
• Filed: 03/13/2013
• Issued: 07/04/2017
• Est. Priority Date: 06/02/2009
• Status: Active Grant

• Current Assignee: LCP Medical Technologies Incorporated
• Original Assignee: HSIO Technologies LLC
• Inventors: Rathburn, James
• Primary Examiner(s): Phan, Thiem
• Application Number:
  US14/408,205
• Publication Number:
  US 20150181710A1
• Time in Patent Office: 1,574 Days
• Field of Search: 29846, 29825, 29829, 29840, 29847, 29852
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/0216 Reduction of cross-talk, noise or electromagnetic interference grounding H05K1/0215
• CPC Class Codes: H05K 1/0256 Electrical insulation details, e.g. around high voltage areas
• CPC Class Codes: H05K 1/0284 Details of three-dimensional rigid printed circuit boards H05K1/119 takes precedence; shaping of the substrate H05K3/0014
• CPC Class Codes: H05K 1/16 incorporating printed electric components, e.g. printed resistor, capacitor, inductor
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/0344 Electroless sublayer, e.g. Ni, Co, Cd or Ag; Transferred electroless sublayer
• CPC Class Codes: H05K 2201/10674 Flip chip
• CPC Class Codes: H05K 2201/10734 Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 3/107 by filling grooves in the support with conductive material H05K3/045, H05K3/101, H05K3/1258 and H05K3/465 take precedence
• CPC Class Codes: H05K 3/4664 Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders H05K3/4647 takes precedence
• CPC Class Codes: H05K 3/4694 Partitioned multilayer circuits having adjacent regions with different properties, e.g. by adding or inserting locally circuit layers having a higher circuit density H05K3/4691 takes precedence
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base

Abstract

A high density region for a low density circuit. At least a first liquid dielectric layer is deposited on the first surface of a first circuitry layer. The dielectric layer is imaged to create plurality of first recesses. Surfaces of the first recesses are plated electro-lessly with a conductive material to form first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. A plating resist is applied. A conductive material is electro-plated to the first conductive structure to substantially fill the first recesses, and the plating resist is removed.

Claims

1. A method of making a high density circuit for a low density circuit comprising the steps of:

depositing at least a first liquid dielectric layer on the first surface of a first circuitry layer to include a plurality of first recesses;

processing selected surfaces of the first recesses to accept electro-less conductive plating deposition;

depositing conductive plating electro-lessly on the selected surfaces of the first recesses comprising a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer;

applying a plating resist to the high density circuit;

substantially filling the first recesses with a conductive material using electro-deposit plating; and

removing the plating resist.

2. The method of claim 1 comprising the steps of:

depositing at least a second liquid dielectric layer on the first dielectric layer to include a plurality of second recesses generally aligned with a plurality of the first conductive structures;

processing selected surfaces of the second recesses to accept electro-less conductive plating deposition;

depositing a conductive material electro-lessly on the selected surfaces of the second recesses comprising a plurality of second conductive structures electrically coupled to, and extending generally perpendicular to, the first conductive structures;

applying a plating resist to the high density circuit;

substantially filling the second recesses with a conductive material using electro-deposit plating; and

removing the plating resist.

3. The method of claim 2 comprising planarizing the first dielectric layer and the first conductive structures before depositing the second dielectric layer.

4. The method of claim 2 comprising electrically coupling contact pads on an IC device to a plurality of the second conductive structures.

5. The method of claim 2 comprising the steps of:

locating a second circuitry layer on the second dielectric layer to electrically couple the second circuitry layer with a plurality of the second conductive structures; and

depositing a third dielectric layer on the second dielectric layer to include a plurality of third recesses generally aligned with a plurality of the second conductive structures.

6. The method of claim 5 comprising etching away portions of the second circuitry layer located in the third recesses to expose a plurality of the second conductive structures.

7. The method of claim 6 comprising the steps of:

plating a conductive material on surfaces of a plurality of the third recesses comprising a plurality of third conductive structure electrically coupled to, and extending parallel to the second conductive structures; and

electrically coupling contact pads on an IC device to a plurality of the third conductive structures, wherein the step of electrically coupling comprises one of a flip chip attachment directly to a plurality of third conductive structures, solder balls, or wire bonding.

8. The method of claim 1 comprising constructing the high density circuit directly on the low density circuit or as a discrete structure.

9. The method of claim 1 comprising the steps of:

forming the first circuitry layer on the low density circuit; and

constructing the high density circuit directly on the low density circuit.

10. The method of claim 1 comprising depositing a dielectric material in one or more of the recesses to surround one or more of the conductive structures.

11. The method of claim 1 comprising printing at least one electrical device on one of the dielectric layers and electrically coupling the electrical device to at least a portion of the circuitry layers.