Multiple engine sequencer

• US 9,702,305 B2
• Filed: 04/17/2013
• Issued: 07/11/2017
• Est. Priority Date: 04/17/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Radke, William H., Borbely, Laszlo, Pruett, David Christopher
• Primary Examiner(s): Sun, Michael
• Application Number:
  US13/864,413
• Publication Number:
  US 20140316684A1
• Time in Patent Office: 1,546 Days
• Field of Search: None
• CPC Class Codes: F02D 25/00 Controlling two or more co-operating engines
• CPC Class Codes: G06F 13/1668 Details of memory controller

Abstract

Multiple engine sequencers in memory interfaces are disclosed. Individual sequencer engines of multiple engine sequencers perform at least portions of their respective operations in parallel with other individual sequencer engine operations performed in the memory interface. In at least one embodiment, sequencer engine operations are performed at least partially concurrently with other sequencer engine operations in the memory interface.

Claims

1. A multiple engine sequencer, comprising:

a first engine to facilitate transfer of data across a first interface for transfer of the data to or from a memory device;

a second engine, different from the first engine, to facilitate transfer of data from a second interface to the first interface for transfer of the data to the memory device;

a third engine, different from the first engine and the second engine, to facilitate transfer of data from the first interface to the second interface for transfer of the data from the memory device; and

a flow control engine in communication with the first engine, the second engine and the third engine, wherein the flow control engine is configured to determine if performance of at least a portion of a memory operation corresponding to a command received at the multiple engine sequencer should be delegated to a different engine of the multiple engine sequencer selected from a group consisting of the first engine, the second engine and the third engine.

2. The multiple engine sequencer of claim 1, wherein the flow control engine is configured to perform at least one of a branch operation, a jump operation and a comparison operation.

3. The multiple engine sequencer of claim 1, wherein the flow control engine being configured to determine if performance of at least a portion of a memory operation should be delegated to a different engine of the multiple engine sequencer comprises the flow control engine being configured to determine if the portion of the memory operation should be performed by the flow control engine or if performance of the portion of the memory operation should be delegated to the different engine.

4. The multiple engine sequencer of claim 1, wherein the flow control engine is further configured to activate the different engine responsive to determining that performance of the at least a portion of the memory operation should be delegated to the different engine.

5. The multiple engine sequencer of claim 1, wherein the flow control engine is further configured to initiate performance of the at least a portion of the memory operation by the different engine responsive to determining that performance of the at least a portion of the memory operation should be delegated to the different engine.

6. The multiple engine sequencer of claim 1, wherein the flow control engine is further configured to inhibit the different engine from completing the at least a portion of the memory operation after performance of the at least a portion of the memory operation has been initiated.

7. The multiple engine sequencer of claim 1, wherein the first engine comprises a crossbar engine.

8. The multiple engine sequencer of claim 1, wherein the second engine comprises a read pipe engine.

9. The multiple engine sequencer of claim 1, wherein the third engine comprises an Open NAND Flash Interface (ONFI) engine.

10. The multiple engine sequencer of claim 1, wherein the first interface is an interface for communication with a crossbar switch and the second interface is an interface for communication with the memory device.

11. A multiple engine sequencer, comprising:

a flow control engine responsive to a received command to perform an operation;

a first additional engine configured to perform a first portion of the operation responsive to one or more first commands from the flow control engine; and

a second additional engine configured to perform a second portion of the operation responsive to one or more second commands from the flow control engine;

wherein the first additional engine and the second additional engine are configured to at least partially perform their respective portions of the operation at least partially in parallel; and

wherein the flow control engine is configured to inhibit the second additional engine from performing the second portion of the operation to completion until a time subsequent to the completion of the first portion of the operation.

12. The multiple engine sequencer of claim 11, wherein the multiple engine sequencer is configured to delegate performance of the first portion of the operation to the first additional engine and to delegate performance of the second portion of the operation to the second additional engine.

13. The multiple engine sequencer of claim 11, wherein the flow control engine is configured to perform a third portion of the operation and further wherein the first additional engine, second additional engine and flow control engine are configured to perform their respective portions of the operation at least partially in parallel.

14. The multiple engine sequencer of claim 11, wherein the multiple engine sequencer is configured to initiate performance of the second portion of the operation after initiation of the first portion of the operation and prior to completion of the first portion of the operation.

15. The multiple engine sequencer of claim 11, wherein the multiple engine sequencer is configured to initiate performance of the second portion of the operation concurrently with the completion of the first portion of the operation.

16. The multiple engine sequencer of claim 11, wherein the multiple engine sequencer is configured to initiate performance of the second portion of the operation in response to a delay during performance of the first portion of the operation.

17. The multiple engine sequencer of claim 16, wherein the multiple engine sequencer being configured to initiate performance of the second portion of the operation in response to a delay during performance of the first portion of the operation comprises the flow control engine being configured to initiate performance of the second portion of the operation at substantially a same time as the delay is expected to occur during the performance of the first portion of the operation.

18. The multiple engine sequencer of claim 16, wherein the multiple engine sequencer being configured to initiate performance of the second portion of the operation in response to a delay during performance of the first portion of the operation comprises the flow control engine being configured to initiate performance of the second portion of the operation at a time prior to completion of the first portion of the operation.

19. The multiple engine sequencer of claim 11, wherein the flow control engine is configured to determine which of the engines will be selected to facilitate performing a memory operation corresponding to the received command.

20. The multiple engine sequencer of claim 11, wherein the first portion of the operation is different than the second portion of the operation.

21. A memory interface, comprising:

a first sequencer engine, wherein the first sequencer engine is configured to perform a first operation;

a second sequencer engine different from the first sequencer engine, wherein the second sequencer engine is configured to perform a second operation; and

a third sequencer engine different from the first sequencer engine and the second sequencer engine, wherein the third sequencer engine is configured to initiate performance of the first operation by the first sequencer engine, and is configured to initiate performance of the second operation by the second sequencer engine in response to an operational delay which occurs during performance of the first operation, wherein the operational delay occurs as a result of performing the first operation.

22. The memory interface of claim 21, wherein the operational delay comprises an operational delay expected to occur while the first operation is performed.

23. The memory interface of claim 21, wherein the third sequencer engine is configured to initiate performance of the first operation by the first sequencer engine responsive to a command received from a processor coupled to the memory interface.

24. The memory interface of claim 23, wherein the received command corresponds to a memory operation to be performed in a memory device coupled to the memory interface.

25. The memory interface of claim 21, wherein the third sequencer engine is further configured to inhibit the completion of the second operation prior to the completion of the first operation.

26. The memory interface of claim 21, wherein the first sequencer engine is configured to initiate performance of the first operation in response to activation of the first sequencer engine;

wherein the second sequencer engine is configured to initiate performance of the second operation in response to activation of the second sequencer engine; and

wherein the third sequencer engine is configured to activate the first sequencer engine, and is configured to activate the second sequencer engine in response to the operational delay.

27. The memory interface of claim 21, further comprising a data pipeline.

28. The memory interface of claim 27, further comprising a memory interface input and a memory interface output, wherein the data pipeline is coupled between the memory interface input and the memory interface output.

29. The memory interface of claim 27, wherein the operational delay comprises an operational delay which occurs in the data pipeline.

30. The memory interface of claim 27, wherein the data pipeline comprises one of a read data pipeline or a write data pipeline.

31. The memory interface of claim 21, wherein the operational delay comprises one of a data read latency delay or a data write latency delay.

32. The memory interface of claim 21, wherein the third sequencer engine is further configured to enable the second sequencer engine to complete the second operation responsive to the completion of the first operation.

33. The memory interface of claim 21, wherein each of the first, second and third sequencer engines are configured to operate concurrently with at least one other of the first, second and third sequencer engines.

34. The memory interface of claim 21, further comprising:

a first interface;

a second interface; and

a RAM memory device coupled to the third sequencer engine.

35. The memory interface of claim 34, further comprising a data pipeline coupled between the first interface and the second interface.

36. The memory interface of claim 34, wherein the first interface comprises a crossbar switch interface.

37. The memory interface of claim 34, wherein the second interface comprises a memory device interface.

38. The memory interface of claim 34, wherein the second interface comprises an Open NAND Flash Interface (ONFI).

39. The memory interface of claim 34, wherein the third sequencer engine is further configured to read one or more commands stored in the RAM memory device and to selectively configure each of the first, second and third sequencer engines responsive to the one or more commands read from the RAM memory device.

40. A method of operating a memory interface, the method comprising:

initiating performance of a first operation by a first sequencer engine; and

initiating performance of a second operation by a second sequencer engine, different from the first sequencer engine, responsive to an operational delay which occurs during performance of the first operation;

wherein performance of the first operation includes fetching data for transfer of the fetched data to or from a memory device coupled to the memory interface;

wherein performance of the second operation includes transferring the fetched data across a read pipeline of the memory interface when the transfer of the fetched data is from the memory device, and transferring the fetched data across a write pipeline of the memory interface when the transfer of the fetched data is to the memory device; and

wherein the performance of the second operation is initiated from a time when the performance of the first operation is initiated to a time when the operational delay is expected to occur.

41. The method of claim 40, further comprising determining the operational delay prior to initiating performance of the first operation by the first sequencer engine and where the operational delay comprises an expected operational delay.

42. The method of claim 40, wherein initiating performance of the second operation further comprises initiating performance of the second operation concurrently with an occurrence of the operational delay occurring while performing the first operation.

43. The method of claim 40, wherein initiating performance of the first operation further comprises initiating performance of the first operation responsive to a command received from a processor coupled to the memory interface, where the received command corresponds to a memory device operation to be performed in the memory device coupled to the memory interface.

44. The method of claim 43, wherein the received command corresponds to one of a memory device read operation or a memory device write operation.

45. The method of claim 40, wherein initiating performance of the second operation further comprises initiating performance of the second operation concurrently with initiating performance of the first operation.

46. The method of claim 40, wherein initiating performance of the second operation further comprises initiating performance of the second operation concurrently with a start of an occurrence of the operational delay.

47. The method of claim 40, wherein initiating performance of the second operation further comprises initiating performance of the second operation subsequent to initiating performance of the first operation.

48. The method of claim 40, further comprising inhibiting the second sequencer engine from completing the second operation prior to completing the first operation.

49. The method of claim 40, further comprising initiating performance of a third operation by a third sequencer engine responsive to the operational delay which occurs during performance of the first operation.

50. The method of claim 40, further comprising initiating performance of a third operation by a third sequencer engine responsive to a different operational delay which occurs during performance of the second operation.