Peripheral clock management

• US 9,703,313 B2
• Filed: 09/15/2015
• Issued: 07/11/2017
• Est. Priority Date: 10/20/2014
• Status: Active Grant

• Current Assignee: Ambiq Micro, Inc.
• Original Assignee: Ambiq Micro, Inc.
• Inventors: Sheafor, Stephen James
• Primary Examiner(s): DONOVAN, LINCOLN D
• Assistant Examiner(s): Mattison, David
• Application Number:
  US14/855,105
• Publication Number:
  US 20160109898A1
• Time in Patent Office: 665 Days
• Field of Search: 327141
• CPC Class Codes: G01R 19/0084 measuring voltage only all subgroups of G01R19/00 take precedence
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/3041 where the computing system component is an input/output interface interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units G06F13/00
• CPC Class Codes: G06F 11/3414 Workload generation, e.g. scripts, playback
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: H02M 1/0045 Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/181 a numerical count result being used for locking the loop, the counter counting during fixed time intervals H03L7/1806 takes precedence
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A clock generator for use in an electronic system comprising an integrated circuit such as a microcontroller. A plurality of oscillators are selectively enabled to produce a respective plurality of oscillator signals. For each of a plurality of clock outputs, a mux selects a respective one of the oscillator signals in response to a respective select signal provided by a clocked facility. The selected oscillator signal is gated out as the respective clock signal in response to a respective gate signal also provided by the clocked facility.

Claims

1. A clock management method for use in a system comprising m clocked facilities, the method comprising the steps of:

[1.1] developing n oscillation signals;

[1.2] receiving a select signal from each of the clocked facilities;

[1.3] selecting a respective one of said n oscillation signals in response to each select signal;

[1.4] receiving an enable signal from each of the clocked facilities; and

[1.5] providing to each of the clocked facilities a clock signal comprising the selected oscillation signal in response to a respective enable signal.

2. The method of claim 1 wherein step [1.1] is further characterized as comprising the step of:

[1.1] selectively developing n oscillation signals.

3. The method of claim 1 wherein step [1.1] is further characterized as comprising the step of:

[1.1] selectively developing each of n oscillation signals only in response to receiving a respective select signal.

4. The method of claim 1 wherein step [1.1] is further characterized as comprising the step of:

[1.1] enabling each of n oscillators adapted to develop respective oscillation signals;

the method further comprising the step of;

[1.6] disabling each of n oscillators if the respective oscillation signal is not selected by a respective select signal.

9. A clock management facility configured to perform the method of any preceding claim.

10. An electronic system comprising a clock management facility according to claim 9.

11. A non-transitory computer readable medium including executable instructions which, when executed in a processing system, causes the processing system to perform the steps of a method according to any one of claims 1 to 8.

5. A clock management method for use in a system comprising m clocked facilities, the method comprising the steps of:

[1.1] disabling n oscillators, each adapted to develop a respective one of n oscillation signals;

[1.2] receiving an assertion of a select signal from each of the clocked facilities;

[1.3] enabling a respective one of said n oscillators to develop a respective oscillation signal in response to each asserted select signal;

[1.4] receiving an assertion of an enable signal from each of the clocked facilities; and

[1.5] providing to each of the clocked facilities a clock signal comprising the selected oscillation signal in response to the assertion of a respective enable signal.

6. The method of claim 5 further characterized as comprising the step of:

[1.6] ceasing to provide to each of the clocked facilities said clock signal in response to a negation of said respective enable signal.

7. The method of claim 6 further characterized as comprising the step of:

[1.7] disabling the respective one of said n oscillators in response to a negation of said respective select signal.

8. The method of claim 5 further characterized as comprising the step of:

[1.6] disabling the respective one of said n oscillators in response to a negation of said respective select signal.