Method and apparatus for power control

• US 9,703,351 B2
• Filed: 09/17/2014
• Issued: 07/11/2017
• Est. Priority Date: 01/28/2010
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Cavium, LLC (Marvell Technology Group Limited)
• Inventors: Carlson, David A., Kessler, Richard E.
• Primary Examiner(s): PATEL, NITIN C
• Application Number:
  US14/488,724
• Publication Number:
  US 20150012764A1
• Time in Patent Office: 1,028 Days
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 11/3058 Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations thermal management in cooling arrangements of a computing system G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y10S 323/907 Temperature compensation of semiconductor

Abstract

Embodiments of the present invention relate to limiting maximum power dissipation occurred in a processor. Therefore, when an application that requires excessive amounts of power is being executed, the execution of the application may be prevented to reduce dissipated or consumed power.

Claims

1. A method comprising:

operatively coupling a temperature sensor chip to a computer chip, the computer chip including multiple processing cores each associated with a field value of a Configuration Status Register (CSR) indicating a maximum power consumption limit for the respective processing core;

tracking the temperature of the computer chip by monitoring temperature sensed by the temperature sensor chip; and

reducing performance in the computer chip to reduce temperature of the computer chip in an event the monitored temperature exceeds a threshold, wherein reducing the performance includes dynamically adjusting the field value of the CSR associated with at least one of the multiple processing cores in the event the monitored temperature exceeds the predetermined threshold.

2. The method of claim 1 wherein the temperature is a junction temperature of the computer chip.

3. The method of claim 1 wherein reducing performance in the computer chip includes preventing events from being processed in the computer chip to reduce temperature of the computer chip.

4. The method of claim 3 wherein preventing events from being processed in the computer chip to reduce temperature of the computer chip includes preventing instructions from being processed.

5. The method of claim 1 wherein reducing performance in the computer chip includes reducing the rate at which further events are processed in the computer chip.

6. An apparatus comprising:

a diode interface operatively coupled to a thermal diode of a computer chip and to a temperature sensor chip external to the computer chip, the computer chip including multiple processing cores each associated with a field value of a Configuration Status Register (CSR) indicating a maximum power consumption limit for the respective processing core;

a temperature monitor module operatively coupled to the temperature sensor chip to track temperature of the computer chip by monitoring temperature sensed by the temperature sensor chip via the diode interface; and

a performance reduction module operatively coupled to the temperature monitor module to receive information to reduce performance in the computer chip to reduce temperature of the computer chip in an event the monitored temperature exceeds a threshold, wherein the performance reduction module dynamically adjusts the field value of the CSR associated with at least one of the multiple processing cores in the event the monitored temperature exceeds the predetermined threshold.

7. The apparatus of claim 6 wherein the temperature is a junction temperature of the computer chip.

8. The apparatus of claim 6 wherein the performance reduction module reduces performance by preventing events from being processed in the computer chip to reduce temperature of the computer chip.

9. The apparatus of claim 8 wherein preventing events from being processed in the computer chip to reduce temperature of the computer chip includes preventing instructions from being processed.

10. The apparatus of claim 6 wherein the performance reduction module reduces performance by reducing the rate at which further events are processed in the computer chip.

11. A method comprising:

operatively coupling a temperature sensor chip to a computer chip, the computer chip including multiple processing cores each associated with a field value of a Configuration Status Register (CSR) indicating a maximum power consumption limit for the respective core;

tracking the temperature of the computer chip by monitoring temperature sensed by the temperature sensor chip; and

reducing power consumption of the chip to reduce temperature of the computer chip in an event the monitored temperature exceeds a threshold, wherein reducing the power consumption includes dynamically adjusting the field value of the CSR associated with at least one of the multiple processing cores in the event the monitored temperature exceeds the predetermined threshold.

12. The method of claim 11 wherein the temperature is a junction temperature of the computer chip.

13. The method of claim 11 wherein reducing power consumption includes preventing events from being processed in the computer chip.

14. The method of claim 11 wherein reducing power consumption includes reducing the rate at which further events are processed in the computer chip.

15. The method of claim 11 further comprising, after reducing power consumption, restoring full power operation to the computer chip upon the monitored temperature falling below the threshold.