Rotational graphics sub-slice and execution unit power down to improve power performance efficiency
First Claim
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1. A processor comprising:
- computational logic having a plurality of slices, wherein each of the plurality of slices is to comprise a plurality of sub-slices to perform one or more computations related to one or more graphics operations; and
logic to cause rotation of power-gating amongst single sub-slices within each slice of the plurality of slices based on an indication to reduce power consumption of the computational logic, wherein the indication to reduce power consumption of the computational logic is to be generated based at least in part on a ratio of leakage power and dynamic power, wherein the one or more graphics operations are to be performed on a plurality of frames, wherein logic to cause rotation of the power-gating is to cause the rotation of the power-gating partway through a frame or at a frame boundary, wherein residency in each rotation of power-gating is capable to differ for each of the sub-slices, wherein logic to cause rotation of power-gating amongst single sub-slices within each slice of the plurality of slices is to cause each powered down single sub-slice within each slice of the plurality of slices to be powered up in response to expiration of a timer.
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Abstract
Methods and apparatus relating to rotational graphics sub-slice and Execution Unit (EU) power down to improve power performance efficiency are described. In one embodiment, power-gating is rotated amongst single sub-slices within each slice of a plurality of slices based on an indication to reduce power consumption of a computational logic. The computational logic includes the plurality of slices and each of the plurality of slices includes a plurality of sub-slices to perform one or more computations. Other embodiments are also disclosed and claimed.
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Citations
26 Claims
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1. A processor comprising:
- computational logic having a plurality of slices, wherein each of the plurality of slices is to comprise a plurality of sub-slices to perform one or more computations related to one or more graphics operations; and
logic to cause rotation of power-gating amongst single sub-slices within each slice of the plurality of slices based on an indication to reduce power consumption of the computational logic, wherein the indication to reduce power consumption of the computational logic is to be generated based at least in part on a ratio of leakage power and dynamic power, wherein the one or more graphics operations are to be performed on a plurality of frames, wherein logic to cause rotation of the power-gating is to cause the rotation of the power-gating partway through a frame or at a frame boundary, wherein residency in each rotation of power-gating is capable to differ for each of the sub-slices, wherein logic to cause rotation of power-gating amongst single sub-slices within each slice of the plurality of slices is to cause each powered down single sub-slice within each slice of the plurality of slices to be powered up in response to expiration of a timer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
- computational logic having a plurality of slices, wherein each of the plurality of slices is to comprise a plurality of sub-slices to perform one or more computations related to one or more graphics operations; and
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12. A method comprising:
- rotating power-gating amongst single sub-slices within each slice of a plurality of slices based on an indication to reduce power consumption of a computational logic, wherein the computational logic comprises the plurality of slices and wherein each of the plurality of slices comprises a plurality of sub-slices to perform one or more computations related to one or more graphics operations, wherein the indication to reduce power consumption of the computational logic is generated based at least in part on a ratio of leakage power and dynamic power, wherein the one or more graphics operations are performed on a plurality of frames, wherein the rotation of the power-gating occurs partway through a frame or at a frame boundary, wherein residency in each rotation of power-gating is capable to differ for Title;
ROTATIONAL GRAPHICS SUB-SLICE AND EXECUTION UNIT POWER DOWN TO IMPROVE POWER PERFORMANCE each of the sub-slices, wherein each powered down single sub-slice within each slice of the plurality of slices is caused to power up in response to expiration of a timer. - View Dependent Claims (13, 14)
- rotating power-gating amongst single sub-slices within each slice of a plurality of slices based on an indication to reduce power consumption of a computational logic, wherein the computational logic comprises the plurality of slices and wherein each of the plurality of slices comprises a plurality of sub-slices to perform one or more computations related to one or more graphics operations, wherein the indication to reduce power consumption of the computational logic is generated based at least in part on a ratio of leakage power and dynamic power, wherein the one or more graphics operations are performed on a plurality of frames, wherein the rotation of the power-gating occurs partway through a frame or at a frame boundary, wherein residency in each rotation of power-gating is capable to differ for Title;
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15. A system comprising:
- a processor having one or more processor cores;
memory to store data to be accessed by at least one of the one or more processor cores;
the processor comprising;
computational logic having a plurality of slices, wherein each of the plurality of slices is to comprise a plurality of sub-slices to perform one or more computations related to one or more graphics operations; and
logic to cause rotation of power-gating amongst single sub-slices within each slice of the plurality of slices based on an indication to reduce power consumption of the computational logic, wherein the indication to reduce power consumption of the computational logic is to be generated based at least in part on a ratio of leakage power and dynamic power, wherein the one or more graphics operations are to be performed on a plurality of frames, wherein logic to cause rotation of the power-gating is to cause the rotation of the power-gating partway through a frame or at a frame boundary, wherein residency in each rotation of power-gating is capable to differ for each of the sub-slices, wherein logic to cause rotation of power-gating amongst single sub-slices within each slice of the plurality of slices is to cause each powered down single sub-slice within each slice of the plurality of slices to be powered up in response to expiration of a timer. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23)
- a processor having one or more processor cores;
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24. A non-transitory computer-readable medium comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to:
- rotate power-gating amongst single sub-slices within each slice of a plurality of slices based on an indication to reduce power consumption of a computational logic, wherein the computational logic comprises the plurality of slices and wherein each of the plurality of slices comprises a plurality of sub-slices to perform one or more computations related to one or more graphics operations, wherein the indication to reduce power Title;
ROTATIONAL GRAPHICS SUB-SLICE AND EXECUTION UNIT POWER DOWN TO IMPROVE POWER PERFORMANCE consumption of the computational logic is to be generated based at least in part on a ratio of leakage power and dynamic power, wherein the one or more graphics operations are performed on a plurality of frames, wherein the rotation of the power-gating occurs partway through a frame or at a frame boundary, wherein residency in each rotation of power-gating is capable to differ for each of the sub-slices, wherein one or more instructions, when executed on the processor, are to configure the processor to cause each powered down single sub-slice within each slice of the plurality of slices to be powered up in response to expiration of a timer. - View Dependent Claims (25, 26)
- rotate power-gating amongst single sub-slices within each slice of a plurality of slices based on an indication to reduce power consumption of a computational logic, wherein the computational logic comprises the plurality of slices and wherein each of the plurality of slices comprises a plurality of sub-slices to perform one or more computations related to one or more graphics operations, wherein the indication to reduce power Title;
Specification