Semiconductor storage device with volatile and nonvolatile memories to allocate blocks to a memory and release allocated blocks

• US 9,703,486 B2
• Filed: 08/10/2015
• Issued: 07/11/2017
• Est. Priority Date: 12/28/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yano, Hirokuni, Kanno, Shinichi, Asano, Shigehiro, Matsuzaki, Hidenori, Kitsunai, Kazuya, Hida, Toshikatsu
• Primary Examiner(s): Verbrugge, Kevin
• Application Number:
  US14/822,138
• Publication Number:
  US 20150347020A1
• Time in Patent Office: 701 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits

Abstract

A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

Claims

1. A semiconductor storage device comprising:

an interface configured to receive data from an external host apparatus;

a nonvolatile semiconductor memory having a plurality of blocks, each of the plurality of blocks being a unit of data erasing, each of the plurality of blocks including a plurality of memory cells, each of the plurality of memory cells being capable of storing two or more bits of data; and

a controller configured to;

selectively allocate a first set of the plurality of blocks as a first memory area;

selectively allocate a second set of the plurality of blocks as a second memory area;

store the data in the first memory area by a first management unit, the first management unit being less than the unit of data erasing;

copy data stored in the first memory area to the second memory area when a condition is satisfied;

manage the first memory area as pseudo SLC (Single level cell) blocks;

manage the second memory area as MLC (Multi level cell) blocks; and

selectively allocate unused blocks for the first memory area or the second memory area.

2. The semiconductor storage device according to claim 1, wherein the controller is configured to determine that the condition is satisfied when a number of valid data stored in at least one of the plurality of blocks in the second first memory area is a first threshold or more.

3. The semiconductor storage device of claim 1, wherein the first and second sets of the plurality of blocks comprise different blocks of the nonvolatile semiconductor memory.

4. The semiconductor storage device of claim 1, wherein the first set of the plurality of blocks selectively allocated for the first memory area comprise at least some blocks of the nonvolatile semiconductor memory that are non-contiguous.

5. The semiconductor storage device of claim 1, wherein the controller is further configured to re-define the first memory area by selectively allocating a third set of the plurality of blocks, the third set of the plurality of blocks being different than the second set of the plurality of blocks.

6. The semiconductor storage device according to claim 1, wherein the nonvolatile semiconductor memory is a NAND type flash memory.

7. The semiconductor storage device according to claim 1, wherein the controller is configured to:

manage the first memory area by the first management unit; and

manage the second memory area by a second management unit, the second management unit being more than the first management unit.

8. A method of controlling a semiconductor storage device, the semiconductor storage device including a nonvolatile semiconductor memory, the nonvolatile semiconductor memory having a plurality of blocks, each of the plurality of blocks being a unit of data erasing, each of the plurality of blocks including a plurality of memory cells, each of the plurality of memory cells being capable of storing two or more bits of data, the method comprising:

selectively allocating a first set of the plurality of blocks as a first memory area;

selectively allocating a second set of the plurality of blocks as a second memory area;

receiving data from an external host apparatus;

storing the data in the first memory area by a first management unit, the first management unit being less than the unit of data erasing;

copying data stored in the first memory area to the second memory area when a condition is satisfied;

manage the first memory area as pseudo SLC (Single level cell) blocks;

manage the second memory area as MLC (Multi level cell) blocks; and

selectively allocating unused blocks for the first memory area or the second memory area.

9. The method according to claim 8, further comprising:

determining that the condition is satisfied when a number of valid data stored in at least one of the plurality of blocks in the first memory area is a first threshold or more.

10. The method according to claim 8, wherein the first and second sets of the plurality of blocks comprise different blocks of the nonvolatile semiconductor memory.

11. The method according to claim 8, wherein the first set of the plurality of blocks selectively allocated for the first memory area comprises at least some blocks of the nonvolatile semiconductor memory that are non-contiguous.

12. The method according to claim 8, further comprising:

re-defining the first memory area by selectively allocating a third set of the plurality of blocks, the third set of the plurality of blocks being different than the second set of the plurality of blocks.

13. The method according to claim 8, wherein the nonvolatile semiconductor memory is a NAND type flash memory.

14. The method according to claim 8, wherein the method comprises:

managing the first memory area by the first management unit; and

managing the second memory area by a second management unit, the second management unit being more than the first management unit.

15. A semiconductor storage device comprising:

an interface configured to receive data from an external host apparatus;

a volatile semiconductor memory including a first memory area;

a nonvolatile semiconductor memory having a plurality of blocks, each of the plurality of blocks having a plurality of pages, each of the plurality of blocks being a unit of data erasing; and

a controller is configured to;

selectively allocate a first set of the plurality of blocks as a second memory area;

selectively allocate a second set of the plurality of blocks as a third memory area;

store the data in the first memory area by a first management unit or less, the first management unit being an access unit from the external host apparatus;

store data outputted from the first memory area in the second memory area by a second management unit, the second management unit being twice or larger natural number times as large as the first management unit and being less than the unit of data erasing;

copy data stored in the second memory area to the third memory area when a condition is satisfied; and

selectively allocate unused blocks for the second memory area or the third memory area.

16. The semiconductor storage device according to claim 15, wherein the controller is configured to:

count a number of data of the first management unit which is stored in the first memory area;

store data outputted from the first memory area by the second management unit in the second memory area when the counted number is less than a first threshold; and

store data outputted from the first memory area by the third management unit in the third memory area when the counted number is equal to the first threshold or more.

17. The semiconductor storage device according to claim 15, wherein the controller is configured to determine that the condition is satisfied when a number of valid data stored in at least one of the plurality of blocks in the second memory area is a first threshold or more.

18. The semiconductor storage device according to claim 15, wherein the first and second sets of the plurality of blocks comprise different blocks of the nonvolatile semiconductor memory.

19. The semiconductor storage device according to claim 15, wherein the first set of the plurality of blocks selectively allocated for the second memory area comprise at least some blocks of the nonvolatile semiconductor memory that are non-contiguous.

20. The semiconductor storage device according to claim 15, wherein the controller is further configured to re-define the second memory area by selectively allocating a third set of the plurality of blocks, the third set of the plurality of blocks being different than the second set of the plurality of blocks.