Vector galois field multiply sum and accumulate instruction

• US 9,703,557 B2
• Filed: 11/16/2014
• Issued: 07/11/2017
• Est. Priority Date: 01/23/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bradbury, Jonathan D.
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US14/542,631
• Publication Number:
  US 20150074383A1
• Time in Patent Office: 968 Days
• Field of Search: None
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30038 using a mask
• CPC Class Codes: G06F 9/30149 of variable length instructions
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format

Abstract

A Vector Galois Field Multiply Sum and Accumulate instruction. Each element of a second operand of the instruction is multiplied in a Galois field with the corresponding element of the third operand to provide one or more products. The one or more products are exclusively ORed with each other and exclusively ORed with a corresponding element of a fourth operand of the instruction. The results are placed in a selected operand.

Claims

1. A method of executing a machine instruction in a central processing unit, the method comprising:

obtaining, by a processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising;

at least one opcode field to provide an opcode, the opcode identifying a Vector Galois Field Multiply Sum and Accumulate operation;

a first register field to be used to designate a first register, the first register comprising a first operand;

a second register field to be used to designate a second register, the second register comprising a second operand;

a third register field to be used to designate a third register, the third register comprising a third operand;

a fourth register field to be used to designate a fourth register, the fourth register comprising a fourth operand; and

a mask field to specify a size of elements of one or more of the first operand, the second operand, the third operand or the fourth operand, wherein the mask field specifies the size of the elements of the second operand and the third operand; and

executing the machine instruction, the executing comprising;

multiplying one or more elements of the second operand with one or more elements of the third operand using carryless multiplication to obtain a plurality of products;

performing a first mathematical operation on the plurality of products to obtain a first result;

performing a second mathematical operation on the first result and one or more selected elements of the fourth operand to obtain a second result; and

placing the second result in the first operand.

2. The method of claim 1, wherein the multiplying comprises multiplying each element of the second operand with the corresponding element of the third operand using carryless multiplication resulting in even-odd pairs of double element-sized products.

3. The method of claim 2, wherein the carryless multiplication has an order of two.

4. The method of claim 2, wherein the first mathematical operation comprises an exclusive OR operation, and wherein the even-odd pairs of double element-sized products are exclusive ORed with each other to obtain the first result.

5. The method of claim 4, wherein the second mathematical operation comprises an exclusive OR operation, and wherein the first result is exclusive ORed with a corresponding double-wide element of the fourth operand to obtain the second result.

6. The method of claim 5, wherein the placing comprises placing the second result in a double-wide element of the first operand.

7. The method of claim 1, wherein the size of the elements of the first operand and the fourth operand are double the size of the elements of the second operand and the third operand.

8. The method of claim 1, wherein the machine instruction further comprises an extension field to be used in designating one or more registers, and wherein the first register field is combined with a first portion of the extension field to designate the first register, the second register field is combined with a second portion of the extension field to designate the second register, the third register field is combined with a third portion of the extension field to designate the third register and the fourth register field is combined with a fourth portion of the extension field to designate the fourth register.

9. A method of executing a machine instruction in a central processing unit, the method comprising:

obtaining, by a processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising;

at least one opcode field to provide an opcode, the opcode identifying a Vector Galois Field Multiply Sum and Accumulate operation;

a first register field to be used to designate a first register, the first register comprising a first operand;

a second register field to be used to designate a second register, the second register comprising a second operand;

a third register field to be used to designate a third register, the third register comprising a third operand;

a fourth register field to be used to designate a fourth register, the fourth register comprising a fourth operand; and

an extension field to be used in designating one or more registers, wherein the first register field is combined with a first portion of the extension field to designate the first register, the second register field is combined with a second portion of the extension field to designate the second register, the third register field is combined with a third portion of the extension field to designate the third register, and the fourth register field is combined with a fourth portion of the extension field to designate the fourth register; and

executing the machine instruction, the executing comprising;

multiplying one or more elements of the second operand with one or more elements of the third operand using carryless multiplication to obtain a plurality of products;

performing a first mathematical operation on the plurality of products to obtain a first result;

performing a second mathematical operation on the first result and one or more selected elements of the fourth operand to obtain a second result; and

placing the second result in the first operand.

10. The method of claim 9, wherein the multiplying comprises multiplying each element of the second operand with the corresponding element of the third operand using carryless multiplication resulting in even-odd pairs of double element-sized products.

11. The method of claim 10, wherein the carryless multiplication has an order of two.

12. The method of claim 10, wherein the first mathematical operation comprises an exclusive OR operation, and wherein the even-odd pairs of double element-sized products are exclusive ORed with each other to obtain the first result.

13. The method of claim 12, wherein the second mathematical operation comprises an exclusive OR operation, and wherein the first result is exclusive ORed with a corresponding double-wide element of the fourth operand to obtain the second result.

14. The method of claim 13, wherein the placing comprises placing the second result in a double-wide element of the first operand.

15. The method of claim 9, wherein a size of elements of the first operand and the fourth operand are double the size of elements of the second operand and the third operand.

16. The method of claim 9, wherein the machine instruction further comprises a mask field to specify a size of elements of one or more of the first operand, the second operand, the third operand or the fourth operand of the machine instruction.

17. The method of claim 9, wherein the machine instruction further comprises a mask field to specify a size of elements of the second operand and the third operand.