Thread transition management

• US 9,703,561 B2
• Filed: 05/11/2014
• Issued: 07/11/2017
• Est. Priority Date: 02/23/2011
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Eisen, Susan E., Kahle, James A., Abernathy, Christopher M., Brown, Mary D., Le, Hung Q., Nguyen, Dung Q.
• Primary Examiner(s): Faherty, Corey S
• Application Number:
  US14/274,752
• Publication Number:
  US 20140258691A1
• Time in Patent Office: 1,157 Days
• Field of Search: None
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/461 Saving or restoring of program or task context

Abstract

Various systems, processes, products, and techniques may be used to manage thread transitions. In particular implementations, a system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination.

Claims

1. A method comprising:

determining that a transition is to be made regarding the relative use of two data register sets, the two data register sets usable by a processor as first-level registers for thread execution in a plurality of different processing modes;

determining, based on the transition determination, whether to move thread data in at least one of the first-level registers to second-level registers;

responsive to determining to move the thread data, assigning a portion of main memory or cache memory as the second-level registers, the second-level registers serving as registers of at least one of the two data register sets for executing a thread in at least one of the plurality of different processing modes; and

moving the thread data from the at least one first-level register to the second-level registers based on the move determination.

2. The method of claim 1, wherein the transition is from a mode in which the data register sets contain mirrored data to one in which they contain different data.

3. The method of claim 2 further comprising:

determining whether starting at least one additional thread is associated with the transition;

maintaining data for existing threads on the first data register set based on an additional thread starting; and

assigning registers on the second data register set to threads being started.

4. The method of claim 1, wherein the transition is from a mode in which the data register sets contain different data to one in which they contain mirrored data.

5. The method of claim 4, further comprising moving the data for active threads from the at least one first-level register to the second-level registers.

6. The method of claim 5, further comprising moving the thread data from the second-level registers to the first-level registers based on use.

7. The method of claim 1, further comprising:

determining whether a thread is starting;

determining, based on a thread starting, whether registers in a data register set may be assigned to the thread; and

assigning the thread second-level registers based on data registers not being assignable to the thread.

8. The method of claim 7, further comprising moving data for the starting thread from the assigned second-level registers to a data register set based on use.

9. The method of claim 1, further comprising:

determining whether a thread is stopping;

determining registers for the stopping thread; and

flushing the registers in a data register set for the stopping thread.

10. The method of claim 1, further comprising:

determining whether an improper imbalance between threads assigned to the data register sets exists;

determining at least one thread to move from one data register set to another data register set;

moving data for the threads to be moved from at least one data register set to second-level registers;

reassigning data register sets for the threads; and

moving data from the second-level registers to the data register sets.

11. A system comprising:

a computer memory;

two data register sets coupled to the computer memory; and

a processor coupled to the two data register sets, the two data register sets usable by the processor as first-level registers for thread execution in a plurality of different processing modes, the processor adapted to;

determine that a transition is to be made regarding the relative use of the data register sets;

determine, based on the transition determination, whether to move thread data in at least one of the first-level registers to second-level registers in the computer memory;

responsive to determining to move the thread data, assign a portion of the computer memory as the second-level registers, the second-level registers serving as registers of at least one of the two data register sets for executing a thread in at least one of the plurality of different processing modes; and

move the thread data from the at least one first-level register to the second-level registers based on the move determination.

12. The system of claim 11, wherein the transition is from a mode in which the data register sets contain mirrored data to one in which they contain different data.

13. The system of claim 12, wherein the processor is further adapted to:

determine whether the starting of at least one additional thread is associated with the transition;

maintain data for existing threads on the first data register set based on an additional thread starting; and

assign registers on the second data register set to threads being started.

14. The system of claim 11, wherein the transition is from a mode in which the data register sets contain different data to one in which they contain mirrored data.

15. The system of claim 14, wherein the processor is further adapted to move the data for active threads from the at least one first-level register to the second-level registers.

16. The system of claim 15, wherein the processor is further adapted to move the thread data from the second-level registers to the first-level registers based on use.

17. The system of claim 11, wherein the processor is further adapted to:

determine whether a thread is starting;

determine, based on a thread starting, whether registers in a data register set may be assigned to the thread; and

assign the thread second-level registers based on data registers not being assignable to the thread.

18. The system of claim 17, wherein the processor is further adapted to move data for the starting thread from the assigned second-level registers to a data register set based on use.

19. The system of claim 11, wherein the processor is further adapted to:

determine whether a thread is stopping;

determine registers for the stopping thread; and

flushing the registers in a data register set for the stopping thread.

20. The system of claim 11, wherein the processor is further adapted to:

determine whether an improper imbalance between threads assigned to the data register sets exists;

determine at least one thread to move from one data register set to another data register set;

move data for the threads to be moved from at least one data register set to second-level registers;

reassign data register sets for the threads; and

move data from the second-level registers to the data register sets.