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Satisfying memory ordering requirements between partial reads and non-snoop accesses

  • US 9,703,712 B2
  • Filed: 12/27/2014
  • Issued: 07/11/2017
  • Est. Priority Date: 07/07/2008
  • Status: Active Grant
First Claim
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1. An apparatus comprising:

  • a receiver to receive a snoop invalidate message, wherein the snoop invalidate message corresponds to a particular cache line; and

    cache protocol logic to generate a writeback message in response to the snoop invalidate message, wherein the writeback message is to indicate a write to a home agent associated with the particular cache line and cause a transition of the particular cache line from a modified cache coherency state to an invalid cache coherency state, the snoop invalidate message comprises a snoop invalidate invalid to exclusive (SnpInvItoE) message, and the SnpInvItoE is to flush any modified state data to the home agent.

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