Satisfying memory ordering requirements between partial reads and non-snoop accesses
First Claim
1. An apparatus comprising:
- a receiver to receive a snoop invalidate message, wherein the snoop invalidate message corresponds to a particular cache line; and
cache protocol logic to generate a writeback message in response to the snoop invalidate message, wherein the writeback message is to indicate a write to a home agent associated with the particular cache line and cause a transition of the particular cache line from a modified cache coherency state to an invalid cache coherency state, the snoop invalidate message comprises a snoop invalidate invalid to exclusive (SnpInvItoE) message, and the SnpInvItoE is to flush any modified state data to the home agent.
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Abstract
A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data.
42 Citations
16 Claims
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1. An apparatus comprising:
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a receiver to receive a snoop invalidate message, wherein the snoop invalidate message corresponds to a particular cache line; and cache protocol logic to generate a writeback message in response to the snoop invalidate message, wherein the writeback message is to indicate a write to a home agent associated with the particular cache line and cause a transition of the particular cache line from a modified cache coherency state to an invalid cache coherency state, the snoop invalidate message comprises a snoop invalidate invalid to exclusive (SnpInvItoE) message, and the SnpInvItoE is to flush any modified state data to the home agent. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An apparatus comprising:
a home agent to; receive a read invalidate message from a first coherency agent, wherein the read invalidate message corresponds to a particular cache line, a snoop invalidate message is to be sent to correspond with the read invalidate message, the snoop invalidate message comprises a snoop invalidate invalid to exclusive (SnpInvItoE); receive a writeback message from a second coherency agent in response to the snoop invalidate message, wherein the writeback message is to cause a transition of the particular cache line from a modified cache coherency state to an invalid cache coherency state; and perform a write to the particular cache line based on the writeback message. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. An apparatus comprising:
a cache coherency agent to; receive a snoop invalidate invalid to exclusive (SnpInvItoE) message, wherein the SnpInvItoE message corresponds to a partial read of a particular cache line by another cache coherency agent and is to flush any modified state data related to the particular cache line to a home agent, and the partial read is to comprise a read invalidate own (RdInvOwn) message; and generate a writeback modified to invalidate (WbMtoI) message in response to the snoop invalidate message, wherein the WbMtoI message is to indicate a writeback of invalid data (WbIData) to the home agent and is to cause a transition of the particular cache line from a modified cache coherency state to an invalid cache coherency state.
Specification